TYOJN5168U0JN5168-001-U00 Wireless USB Dongle

DR1198 JN5168 USB Dongle Reference Manual JN-RM-2065 Revision 1.0 17-Dec-2012 DR1198 JN5168 USB Dongle Reference Manual 2 © NXP Laboratories UK 2012 JN-RM-2065 v1.0 Contents About this Manual 3 Organisation 3 Conventions 3 Acronyms and Abbreviations 3 Related Documents 3 1 Introduction 4 1.1 Overview 4 1.2 Features 5 1.3 Reference Design 5 2 Hardware Overview 6 2.1 Dongle Layout 6 2.2 Dongle Block Diagram 6 2.3 FT232L Device 6 2.4 JN5168 Device 6 2.5 LEDs 7 2.6 32-kHz Crystal Oscillator 7 3 Programming 8 4 Compliance Statements & Documentation 9 4.1 FCC Statements and Documentation 9 4.1.1 Federal Communication Commission Interference Statement 9 4.1.2 WARNING! 9 FCC Radiation Exposure Statement: 9 4.1.3 FCC Declaration of Conformity 10 4.2 Industry Canada Statement 11 4.3 European R & TTE Directive 1999/5/EC Statement 11 DR1198 JN5168 USB Dongle Reference Manual JN-RM-2065 v1.0 © NXP Laboratories UK 2012 3 About this Manual This manual provides a detailed reference for NXP’s DR1198 JN5168 USB Dongle. The manual is part of the reference design JN-RD-6039. This USB Dongle provides an easy way of communicating with the NXP JN5168 wireless microcontroller from a USB connection. With suitable embedded software running on the JN5168 device, the dongle can then communicate with an IEEE 802.15.4, JenNet-IP or ZigBee PRO network. Organisation This manual consists of 4 chapters, as follows:  Chapter 1 outlines the features and functions of the USB dongle  Chapter 2 provides a hardware overview  Chapter 3 describes programming the JN5168 device on the dongle  Chapter 4 contains compliance statements and documentation Conventions Files, folders, functions and parameter types are represented in bold type. Function parameters are represented in italics type. Code fragments are represented in the Courier typeface. Acronyms and Abbreviations BOM Bill Of Materials DIO Digital Input/Output PCB Printed Circuit Board SDK Software Developer’s Kit UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus Related Documents JN-DS-JN5168 JN5168 Data Sheet DR1198 JN5168 USB Dongle Reference Manual 4 © NXP Laboratories UK 2012 JN-RM-2065 v1.0 1 Introduction This manual provides a detailed reference for the DR1198 JN5168 USB Dongle, supplied with JN516x EK001 evaluation kit. The dongle provides a platform for hardware development environment for wireless microcontroller applications with a USB interface. 1.1 Overview The DR1198 JN5168-001-U00 Dongle provides an easy way of interfacing a host machine (such as a PC) to a wireless network based on the IEEE802.15.4, JenNet-IP, ZigBee Light Link, ZigBee Smart Energy and RF4CE networking applications. The dongle incorporates the NXP JN5168 wireless microcontroller, allowing a direct USB connection between the host machine and the JN5168 device, which then provides the radio interface to the wireless network. Typical uses of the dongle include:  A complete and stable hardware environment for the development of IEEE802.15.4, JenNet-IP, ZigBee Light Link, ZigBee Smart Energy and RF4CE networking applications, facilitating an accelerated time- to-market for wireless network products  The basis of a packet sniffer for IEEE 802.15.4-based wireless communications  A means of integrating the host machine into a wireless network, typically as the network Co-ordinator The small-footprint PCB of the dongle provides all the necessary components for a wireless microcontroller with access to a USB connection. All RF layout and decoupling issues are handled by the design of this dongle. Therefore, this design is ready for application development without the necessity of hardware development. The dongle is shown below. DR1198 JN5168 USB Dongle Reference Manual JN-RM-2065 v1.0 © NXP Laboratories UK 2012 5 1.2 Features The dongle has the following features:  USB 2.0 Full-Speed Compatible Interface  IEEE 802.15.4-based wireless microcontroller (JN5168) with the following radio characteristics:  Transmit Power: 2.5 dBm (typ.)  Transmit Current: 15mA (typ.)  Receive Sensitivity: –95dBm (typ.)  Receive Current: 17.5mA (typ.)  Printed RF antenna general-purpose LEDs (one green, one orange)  Serial Flash memory device  32-kHz crystal oscillator 1.3 Reference Design A reference design (JN-RD-6039) for the JN5168 High-Power USB Dongle is available from www.nxp.com/jennic/support. The reference design comprises a ZIP file containing the following files:  This Reference Manual  The schematic diagram for the board  The BOM (Bill Of Materials) for the board  Gerbers for the board DR1198 JN5168 USB Dongle Reference Manual 6 © NXP Laboratories UK 2012 JN-RM-2065 v1.0 2 Hardware Overview 2.1 Dongle Layout 1 6 m m 30mm USB JN5168 LEDS FT232RL Antenna SPI Flash Figure 1: DR1198 Board Layout 2.2 Dongle Block Diagram Timers UART Temp sensor SPI RAM 32kB 128-bit AES Encryption Accelerator 2.4GHz Radio Flash 256kB RISC CPU Power Management XTAL 32.768 kHz O-QPSK Modem IEEE802.15.4 MAC Accelerator 512kB Serial Flash Memory JN5148 chip Integrated Antenna 32kHz ext Xtal Sleep Counters 4kB EEPROM Watchdog timer Time of Flight Engine USB FT232RL XTAL 32 MHz XTAL 12 MHz Matching 2.3 FT232L Device The FT232L device is connected to the USB connector and acts as an interface between the PC and the JN5168 device. The FT232L will enumerate on the PC as a virtual COM port connected directly to UART0 on the JN5168. 2.4 JN5168 Device The JN5168 circuit is based around the standard JN-RD-6038 JN5168 reference design; however it is built on a 2 layer board as the DIOs do not need to be externally available. DR1198 JN5168 USB Dongle Reference Manual JN-RM-2065 v1.0 © NXP Laboratories UK 2012 7 2.5 LEDs There are two surface-mounted LEDs that can be controlled by the JN5148 wireless microcontroller (see Figure 2 for locations):  LED D1 which is green  LED D2 which is orange Both LEDs are connected to DIO16 and DIO17. These DIOs can be used to control the LEDs as indicated in the table bel…

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TRaC Global 100 Frobisher Business Park, Leigh Sinton Road Malvern, Worcestershire, WR14 1BX, UK Date 17 th December, 2012 Letter of Agency To Whom It May Concern: We certify that we are not subject to denial of federal 5301 of the Anti-Drug Abuse ACT of 1988, U.S.C. 862. Further, no party, as defined in 47 CFR 1.2002(b), to the application, is subject to denial of federal benefits, that includes FCC benefits. Thank you for your attention to these matters. Yours faithfully Full Name Mr Conrad V Farlow NXP Laboratories (UK) Ltd We certify that we are not subject to denial of federal benefits that includes FCC benefits, pursuant to Section Drug Abuse ACT of 1988, U.S.C. 862. Further, no party, as defined in 47 CFR 1.2002(b), to the al of federal benefits, that includes FCC benefits. Thank you for your attention to these matters. includes FCC benefits, pursuant to Section Drug Abuse ACT of 1988, U.S.C. 862. Further, no party, as defined in 47 CFR 1.2002(b), to the

NXP Laboratories (UK) Ltd, Furnival Street, Sheffield, Tel: +00 44 114 281 2655, Fax: +00 44 114 281 2951, www.nxp.com TRaC Global 100 Frobisher Business Park, Leigh Sinton Road Malvern, Worcestershire, WR14 1BX, UK Date 18 th December, 2012 TYOJN5168U0 – Operational Description Radio The figure below shows the single ended radio architecture and frequency generating scheme used in the JN5168 chip: Switch TX 2.405 RX 2.4036875 Figure 1: Radio Architecture The radio comprises a low-IF receive path and a direct modulation transmit path, which converge at the TX/RX switch. The switch connects to the external single ended matchin network, which consists of two inductors and a capacitor, this arrangement creates a 50 port and removes the need for a balun. A 50 directly to this port. NXP Laboratories (UK) Ltd, Furnival Street, Sheffield, South Yorkshire, S1 4QT, UK 114 281 2951, www.nxp.com Operational Description The figure below shows the single ended radio architecture and frequency generating scheme used in the JN5168 chip: I L R Lim1Lim2Lim3Lim4 ADC CalibrationMux VCO Synth Sigma Delta 405 – 2.480 GHz 4036875 – 2.4813125 GHz IF 1.3125 MHz XO – 32.000000 MHz IF receive path and a direct modulation transmit path, which converge at the TX/RX switch. The switch connects to the external single ended matchin network, which consists of two inductors and a capacitor, this arrangement creates a 50 removes the need for a balun. A 50Ω single ended antenna can be connected The figure below shows the single ended radio architecture and frequency generating D-Type ADC IF receive path and a direct modulation transmit path, which converge at the TX/RX switch. The switch connects to the external single ended matching network, which consists of two inductors and a capacitor, this arrangement creates a 50Ω single ended antenna can be connected The 32MHz crystal oscillator feeds a divider, which provid reference frequency. The synthesiser contains programmable feedback dividers, phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no external components, and includes calibration ci internal component values due to process and temperature variations. The VCO is controlled by a Phase Locked Loop (PLL) that has an internal loop filter. A programmable charge pump is also used to tune the loop ch The receiver chain starts with the low noise amplifier/mixer combination whose outputs are passed to a low pass filter, which provides the channel definition. The signal is then passed to a series of amplifier blocks forming a limiting strip signal before being passed to the Modem. The gain control for the RX path is derived in the automatic gain control (AGC) block within the Modem, which samples the signal level at various points down the RX chain. T consumption, automatic calibration is applied to various blocks in the RX path. In the transmit direction, the digital stream from the Modem is passed to a digital modulator which controls the feedba The VCO frequency now tracks the applied modulation. then passed to the RF Power Amplifier (PA), whose power control can be selected from one of three settings. The output of the PA drives an external Skyworks Front End Module which houses an LNA, PA and necessary RF switching as shown in figure 2 the module block diagram. RAM 32kB 128-bit AES Encryption Accelerator 2.4GHz Radio Flash 256kB RISC CPU Power Management O-QPSK Modem IEEE802.15.4 MAC Accelerator JN5148 chip Integrated Antenna 4kB EEPROM Watchdog timer Time of Flight Engine USB FT232RL XTAL 32 MHz XTAL 12 MHz Matching Figure 2: Dongle Block diagram The 32MHz crystal oscillator feeds a divider, which provides the frequency synthesiser with a reference frequency. The synthesiser contains programmable feedback dividers, phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no external components, and includes calibration circuitry to compensate for differences in internal component values due to process and temperature variations. The VCO is controlled by a Phase Locked Loop (PLL) that has an internal loop filter. A programmable charge pump is also used to tune the loop characteristic. The receiver chain starts with the low noise amplifier/mixer combination whose outputs are passed to a low pass filter, which provides the channel definition. The signal is then passed to a series of amplifier blocks forming a limiting strip. The signal is converted to a digital signal before being passed to the Modem. The gain control for the RX path is derived in the automatic gain control (AGC) block within the Modem, which samples the signal level at various points down the RX chain. To improve the performance and reduce current consumption, automatic calibration is applied to various blocks in the RX path. In the transmit direction, the digital stream from the Modem is passed to a digital modulator which controls the feedback dividers in the synthesiser, (dual point modulation). The VCO frequency now tracks the applied modulation. The 2.4 GHz signal from the VCO is then passed to the RF Power Amplifier (PA), whose power control can be selected from one The output of the PA drives an external Skyworks Front End Module which houses an LNA, PA and necessary RF switching as shown in figure 2 the module block Timers UART Temp sensor SPI XTAL 32.768 kHz 512kB Serial Flash Memory 32kHz ext Xtal Sleep Counters es the frequency synthesiser with a reference frequency. The synthesiser contains programmable feedback dividers, phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no rcuitry to compensate for differences in internal component values due to process and temperature variations. The VCO is controlled by a Phase Locked Loop (PLL) that has an internal loop filter. A programmable charge pump The receiver chain starts with the low noise amplifier/mixer combination whose outputs are passed to a low pass filter, which provides the c…

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TYOJN5168U0 USB Dongle This document has been generated in support of the FCCID application for the TYOJN5148UØ USB Dongle It covers the following product JN5148-ØØ1-U00 The following picture shows an example of NXP’s JN5148-J01-U00 JN5168-001-UØØ Subsequent to being granted an FCC 001-UØØ. Label line 1: Part Name Industry Canada ID Number Label line 2: FCC ID Number Label line 3: Industry Canada ID Number USB Dongle Labelling This document has been generated in support of the FCCID application for the UØ USB Dongle. It covers the following product: The following picture shows an example of NXP’s USB Dongle labelling UØØ Subsequent to being granted an FCC-ID the following label will be used for Product Identification Instructions Industry Canada ID Number FCC ID Number Industry Canada ID Number This document has been generated in support of the FCCID application for the labelling (this for the ng label will be used for JN5168-

NXP Laboratories (UK) Ltd, Furnival Street, Sheffield, Tel: +00 44 114 281 2655, Fax: +00 44 114 281 2951, www.nxp.com TRaC Global 100 Frobisher Business Park, Leigh Sinton Road Malvern, Worcestershire, WR14 1BX, UK Date 18 th December, 2012 TYOJN5168U0 – Operational Description Radio The figure below shows the single ended radio architecture and frequency generating scheme used in the JN5168 chip: Switch TX 2.405 RX 2.4036875 Figure 1: Radio Architecture The radio comprises a low-IF receive path and a direct modulation transmit path, which converge at the TX/RX switch. The switch connects to the external single ended matchin network, which consists of two inductors and a capacitor, this arrangement creates a 50 port and removes the need for a balun. A 50 directly to this port. NXP Laboratories (UK) Ltd, Furnival Street, Sheffield, South Yorkshire, S1 4QT, UK 114 281 2951, www.nxp.com Operational Description The figure below shows the single ended radio architecture and frequency generating scheme used in the JN5168 chip: I L R Lim1Lim2Lim3Lim4 ADC CalibrationMux VCO Synth Sigma Delta 405 – 2.480 GHz 4036875 – 2.4813125 GHz IF 1.3125 MHz XO – 32.000000 MHz IF receive path and a direct modulation transmit path, which converge at the TX/RX switch. The switch connects to the external single ended matchin network, which consists of two inductors and a capacitor, this arrangement creates a 50 removes the need for a balun. A 50Ω single ended antenna can be connected The figure below shows the single ended radio architecture and frequency generating D-Type ADC IF receive path and a direct modulation transmit path, which converge at the TX/RX switch. The switch connects to the external single ended matching network, which consists of two inductors and a capacitor, this arrangement creates a 50Ω single ended antenna can be connected The 32MHz crystal oscillator feeds a divider, which provid reference frequency. The synthesiser contains programmable feedback dividers, phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no external components, and includes calibration ci internal component values due to process and temperature variations. The VCO is controlled by a Phase Locked Loop (PLL) that has an internal loop filter. A programmable charge pump is also used to tune the loop ch The receiver chain starts with the low noise amplifier/mixer combination whose outputs are passed to a low pass filter, which provides the channel definition. The signal is then passed to a series of amplifier blocks forming a limiting strip signal before being passed to the Modem. The gain control for the RX path is derived in the automatic gain control (AGC) block within the Modem, which samples the signal level at various points down the RX chain. T consumption, automatic calibration is applied to various blocks in the RX path. In the transmit direction, the digital stream from the Modem is passed to a digital modulator which controls the feedba The VCO frequency now tracks the applied modulation. then passed to the RF Power Amplifier (PA), whose power control can be selected from one of three settings. The output of the PA drives an external Skyworks Front End Module which houses an LNA, PA and necessary RF switching as shown in figure 2 the module block diagram. RAM 32kB 128-bit AES Encryption Accelerator 2.4GHz Radio Flash 256kB RISC CPU Power Management O-QPSK Modem IEEE802.15.4 MAC Accelerator JN5148 chip Integrated Antenna 4kB EEPROM Watchdog timer Time of Flight Engine USB FT232RL XTAL 32 MHz XTAL 12 MHz Matching Figure 2: Dongle Block diagram The 32MHz crystal oscillator feeds a divider, which provides the frequency synthesiser with a reference frequency. The synthesiser contains programmable feedback dividers, phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no external components, and includes calibration circuitry to compensate for differences in internal component values due to process and temperature variations. The VCO is controlled by a Phase Locked Loop (PLL) that has an internal loop filter. A programmable charge pump is also used to tune the loop characteristic. The receiver chain starts with the low noise amplifier/mixer combination whose outputs are passed to a low pass filter, which provides the channel definition. The signal is then passed to a series of amplifier blocks forming a limiting strip. The signal is converted to a digital signal before being passed to the Modem. The gain control for the RX path is derived in the automatic gain control (AGC) block within the Modem, which samples the signal level at various points down the RX chain. To improve the performance and reduce current consumption, automatic calibration is applied to various blocks in the RX path. In the transmit direction, the digital stream from the Modem is passed to a digital modulator which controls the feedback dividers in the synthesiser, (dual point modulation). The VCO frequency now tracks the applied modulation. The 2.4 GHz signal from the VCO is then passed to the RF Power Amplifier (PA), whose power control can be selected from one The output of the PA drives an external Skyworks Front End Module which houses an LNA, PA and necessary RF switching as shown in figure 2 the module block Timers UART Temp sensor SPI XTAL 32.768 kHz 512kB Serial Flash Memory 32kHz ext Xtal Sleep Counters es the frequency synthesiser with a reference frequency. The synthesiser contains programmable feedback dividers, phase detector, charge pump and internal Voltage Controlled Oscillator (VCO). The VCO has no rcuitry to compensate for differences in internal component values due to process and temperature variations. The VCO is controlled by a Phase Locked Loop (PLL) that has an internal loop filter. A programmable charge pump The receiver chain starts with the low noise amplifier/mixer combination whose outputs are passed to a low pass filter, which provides the c…

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ItemQTTYComponent ReferenceDescriptionManufacturerManufacturer PartSupplierSupplier PartNotes 14 C8, C11-12, C14Capacitor 47pF 0402 NPOPhyComp(Yageo)223886915479Flint2238-869-15479. 22C1, C13Capacitor 10nF 0402 X7RPhyComp(Yageo)223878715636Farnell InOne301-9275. 36C2, C4-5, C9, C15-16Capacitor 100nF 0402 X5RBourns YageoCC0402AX5R104KTRFlintCC0402AX5R104KTR. 42C3, C10Capacitor 12pF 0402 COGKEMETC0402C120J5GACTUFarnell InOne1414576. 52C6-7Capacitor 15pF 0402 COGKEMETC0402C150J5GACTUFarnell InOne1414577. 61C17Capacitor 10uF 6.3V 0805 X5RKEMETC0805C106K9PACFarnell InOne922-7814. 71D1LED SMD 0603 GREENAVAGO TECHNOLOGIESASMT-RF45-AN002Farnell InOne1652078. 81D2LED SMD 0603 ORANGEAVAGO TECHNOLOGIESASMT-RJ45-AQ502Farnell InOne1710526. 92D3-41PS79SB30NXP1PS79SB30Farnell InOne8734097. 101FE1Ferrite Bead (470R ~ 100MHz)MurataBLM18PG471SN1Farnell InOne1515745. 111L1Inductor 5.1nHmuRataLQP15MN5N1B02Farnell InOne1515367. 121L2Inductor 3.9nH muRataLQP15MN3N9B02Digikey490-1131-1-ND. 131R1Resistor 43K 0402 1%PhyComp(Yageo)232270674303Farnell InOne145-8795 . 141R2Resistor 680R_0402 1%PhyComp(Yageo)232270570681Farnell InOne923-2745. 151J1USB Plug, Type ALUMBERG2410 07Farnell InOne1308875. 161U1IC Serial 3V Flash SMD M25P40-AVMN6PBMicronM25P40-VMN6PBAvnetM25P40-VMN6PB. 171U2FT232RLFTDIFT232RLFarnell InOne1146032. 181U3JN5168NXPJN5168NXPJN5168. 191X2Crystal SMD FC-135 32.768 kHzEPSON TOYOCOM Q13FC1350000301ACALFC-135 32.768 KHz. 201Y1Crystal SMD 32 MHzAELX32M000000S039AAELX32M000000S039A. 210C18Parts Not To Be Fitted..... RevisionDateAssemblyDescription 1V0.123/11/2012DR1198JN5168 USB Dongle ItemQTTYComponent Reference (Second Source)DescriptionManufacturerManufacturer PartSupplierSupplier PartNotes 14 C8, C11-12, C14...... 22C1, C13...... 36C2, C4-5, C9, C15-16...... 42C3, C10...... 52C6-7...... 61C17...... 71D1...... 81D2...... 92D3-4...... 101FE1...... 111L1...... 121L2...... 131R1...... 141R2...... 151J1...... 161U1IC Serial 3V Flash W25X40BLSNIGWinbondW25X40BLSNIGAvnetW25X40BLSNIG. 171U2...... 181U3...... 191X2...... 201Y1Crystal 32 MHz (extended temp)EPSON TOYOCOM X1E000021016700ACALTSX-3225 32MHz. 210C18...... RevisionDateAssemblyDescription 1V0.123/11/2012DR1198JN5168 USB Dongle

Prediction of Distance for a specific MPE Limit TYOJN5168U0 Equation from page 18 of OET Bulletin 65, Edition 97-01 S = power density P = power input to the antenna G = power gain of the antenna in the direction of interest relative to an isotropic radiator R = distance to the centre of radiation of the antenna Max input to antenna terminal 2.8 dBm 1.91 Max Antenna gain 1.1 dBi 1.66 Prediction Freq 2.44 GHz 2.44E+09 MPE limit for uncontrolled exposure at prediction frequency 1 mW/cm 2 Permitted distance at MPE limit (1 mW/cm2) in cm 0.442 S PG R π4 = 2 4R PG S π =

FCC 47CFR part 15C Test Report For DR1198 JN5168-001-U00 USB Dongle DR1198 JN5168-001-U00 Reference Standard: FCC 47CFR part 15C Manufacturer: NXP Laboratories UK Ltd For type of equipment and serial number, refer to section 3 Report Number: 11-6535-4-12 Report Produced by: - R.N. Electronics Ltd. 1 Arnolds Court Arnolds Farm Lane Mountnessing Essex CM13 1UT U.K. www.RNelectronics.com Telephone +44 (0) 1277 352219 Facsimile +44 (0) 1277 352968 electronics R N 2012 RN ELECTRONICS LIMITED REPORT NUMBER 11-6535-4-12 ALL RIGHTS RESERVED File name NXP LABORATORIES UK LTD.6535-4 (FCC RADIO).DOCX The contents of this report, apart from the referenced ANSI C63.4-2003, are beyond the scope of UKAS Testing Laboratory No. 2360 accreditation. QMF21J – 3; 47CFR15.247, RNE ISSUE 01 SEP 2012 PAGE 2 OF 58 Copy No. pdf Arnolds Court, Arnolds Farm Lane, Mountnessing, Brentwood Essex, CM13 1UT Certificate of Test 6535/4 The unit noted below has been tested by R.N. Electronics Limited and, where appropriate, conforms to the relevant subpart of FCC 47CFR Part 15. This is a certificate of test only and should not be confused with an equipment authorisation. Other standards may also apply. Equipment: DR1198 JN5168-001-U00 USB Dongle Model Number: DR1198 JN5168-001-U00 Proposed FCC ID: TYOJN5168U0 Unique Serial Number: 1 Manufacturer: NXP Laboratories UK Ltd Furnival Street Sheffield S1 4QT Customer Purchase Order Number: GB628200059902 Full measurement results are detailed in Report Number: 11-6535-4-12 Test Standards: FCC 47CFR Part 15.247 effective date October 1 st 2012, Class DTS Intentional Radiator NOTE: Certain tests were not performed based upon manufacturer's declarations. Certain other requirements are subject to manufacturer declaration only and have not been tested/verified. For details refer to section 3 of this report. DEVIATIONS: Deviations from the standards have been applied. For details refer to section 4.2 of this report. This certificate relates only to the unit tested as identified by a unique serial number and in the condition at the time it was tested. It does not relate to any other similar equipment and performance of the product before or after the test cannot be guaranteed. Whilst every effort is made to assure quality of testing, type tests are not exhaustive and although no non-conformances may be found, this doesn't exclude the possibility of unit not meeting the intentions of the standard or the requirements of the Directive, particularly under different conditions to those during testing. Any compliance statements are made reliant on (a) the application of the product and use of the assigned band being acceptable to one or more national authorities within the EU and (b) the modes of operation as instructed to us by the Customer based on their specific knowledge of the application and functionality of the EUT. Statements of compliance, where measurements were made, do not include the measurement uncertainty. The measurement uncertainty, where stated, is the expanded uncertainty based on a standard uncertainty multiplied by a coverage factor of k=2, providing a level of confidence of approximately 95%. Date of Test: 1st Nov 2012 - 8th Nov 2012 Test Engineer: Lee Chandler Approved By: Technical Director Customer Representative: electronics R N 2012 RN ELECTRONICS LIMITED REPORT NUMBER 11-6535-4-12 ALL RIGHTS RESERVED File name NXP LABORATORIES UK LTD.6535-4 (FCC RADIO).DOCX The contents of this report, apart from the referenced ANSI C63.4-2003, are beyond the scope of UKAS Testing Laboratory No. 2360 accreditation. QMF21J – 3; 47CFR15.247, RNE ISSUE 01 SEP 2012 PAGE 3 OF 58 1 Contents 1 Contents .............................................................................................................. 3 2 Summary of test results ........................................................................................ 4 3 Equipment Under Test (EUT) ............................................................................... 5 3.1 EQUIPMENT SPECIFICATION .............................................................................................................. 5 3.2 EUT CONFIGURATIONS FOR TESTING ................................................................................................ 5 3.3 FUNCTIONAL DESCRIPTION ............................................................................................................... 6 3.4 EUT MODES ..................................................................................................................................... 6 3.5 EMISSIONS CONFIGURATION ............................................................................................................. 7 4 Specifications ....................................................................................................... 8 4.1 RELEVANT STANDARDS .................................................................................................................... 8 4.2 DEVIATIONS ...................................................................................................................................... 8 4.3 TESTS AT EXTREMES OF TEMPERATURE & VOLTAGE........................................................................ 8 4.4 MEASUREMENT UNCERTAINTIES ...................................................................................................... 8 5 Tests, Methods and Results ................................................................................. 9 5.1 CONDUCTED EMISSIONS .................................................................................................................... 9 5.3 PEAK CONDUCTED POWER .............................................................................................................. 11 5.4 MAXIMUM SPECTRAL POWER DENSITY .......................................................................................... 12 5.5 DUTY CYCLE ......................................................................…

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