VTXSG08Digital Photo Frame

Use’s manual 4.1 Adding new photo album 4.2 Shogo dashboard 4.3 Adding Shogo Authors 4.4 Adding Shogo Friends 4.1 Adding new photo album 4.2 Shogo dashboard 4.3 Adding Shogo Authors 4.4 Adding Shogo Friends

55 44 33 22 11 A A B B C C D D JZ4730 CPU U1 LCD Touch Panel U14 AK4182A Touch Panel Drive U9 AK4387 DAC U10 KB4863 Audio Power Amplifier LR Phone Jack U8 AU6368 Card Read J2 Card Connector J14 USB SLAVE J15 USB HOST AU9254A21 U19 USB HUB Controller U17 RTL8201BL EtherNet U18 TRANSFORMER J13 RJ45 J6 WiFi module WiFi antenna U3 NORFLASH NANDFLASH U4 SDRAM U3 SDRAM U2 KEYBOARD T2 RF Remotecontrol module Real-timeclock/calendar U7 VC8563 K1POWEROFF/ON Powersupply J7POWER JACK U12 RT9501 Battery Charger Battery Adapter 32.768KHz 12MHz Y2 Y1 Y3 12MHz Y5 12MHz Y4 25MHz V2 1 Digital Photo Frame SG080 / SG081 / SG081A Custom 11 Tuesday, January 22, 2008 SHOGO TitleSize Document Number Rev Date: Sheet of

LTffilgffifl RealEase Limited 15/F, Morrison Commercial Building,31 Morison Hill'Road,l{anchai, Hong Kong Tel: (B'D zsTT 8gB3 Fax: (.BgD zsTT 3872 I Declaration of Com'formity We, RealEase Limited hereby declarate the product designded below. Product Name Digital Photo frame Model SG080.SG08 l:SGO8l A ''' Trade Name SHOGO Applicable Standard(s) FCC Part 15 SubpartB Class B(DoC) Report No. S2080122B05-EF i This device has been tested and found to comply with the stated standard(s) ,which is (are) required by the Federal Communications Committee. Daniel Schneersohn/CEO RealEase Limited

EUT EXTERIOR PHOTO Applicant: RealEase Limited FCC ID: VTXSG08

EUT INSIDE PHOTO Applicant: RealEase Limited FCC ID: VTXSG08

Working Principle The Digital Photo Frame consistes RF transceiver/receiver and digital photo processing circuits. 1. The RF transceiver/reciever circuit is composed of RF modul AL2230S and its accessory components . AL2230S is a highly integrated RF transceiver IC for 2.4GHz band 802.11b/g applications , and combines all functions of the transceiver in a single chip. AL2230S also integrates on-chip PA and PLL to help you to minimize the use of external components to design an RF subsystem. The receive path implements a direct down-conversion architecture to eliminate additional IF filters. It includes a single-ended input Low Noise Amplifier (LNA), a direct down-conversion mixer with DC-offset cancellation , and a variable gain amplifier with a baseband low-pass filter. The transmitter consists of a direct up-conversion quadrature modulator with a baseband low pass filter,a variable gain amplifier , a power amplifier and a power detector to complete the whole transmit path function. A power-on calibration procedure is established to corret the TX DC offset and filters mismatch . These functions are housed in a 48-pin QFN package. 2. The digital photo processing circuit is composed of CPU JZ4730 and its accessory components . JZ4730 is the CPU in Digital Photo Frame of mainboard.It’ll be processed theAudio and Video signals through the connector J2. J2 is the connector which connects RF and photo processing circuit .

55 44 33 22 11 A A B B C C D D NAND Flash Place Capacitorsnear the U4 SAMSUNG 128M X 8 BITNAND FLASH MEMORY FOR SDRAM CHIP2FOR SDRAM CHIP1 AMD : (0 ohm)SST : (NC) MEMORY & FLASH 1.0 SHOGO Digital Photo Frame Custom 110 Wednesday, August 15, 2007 TitleSize Document Number Rev Date: Sheet of MA3 MCKE MRAS_N MDCS0_N MDCS0_N MCAS_N MWE3_NMCAS_N MRAS_N MCAS_NMRDWR_N MRDWR_N MRAS_N CLK_MCKO CLK_MCKO MWE0_N MDCS0_N MCKE MCKE MA10 MA10 MWE2_N MWE1_N D26 D26D14 D14 FRB_N FRB_N D17 D17 D11 D11 D9 D9 MA14 MA14MA9MA7 MA7 RAS_N CKE A7 MA4 CKOD29 D29 MA9 D13 D13 MA6 MA6 RDWR_N D7 MA13 MA13 A6 D4 D4 D4 D7 D7 MA12 D27 D27 D2 D2 D2 A9 D15 D15 MA12 D6 D6 D6 D0 D0 D0 MA5 CAS_N DCS0_N D3 D3 D3 MA8 MA8MA5 D5 MA2 MA2 MA11 MA11 D12 D12D8 D8 D5 D5 MA4 MA4 D25 D25 D20 MA15 MA15 DCS0_N CKE D22 D22 D20 RAS_N CAS_N A14 D31 D31D18 D18 D1 CS3_N CS3_N MA3 MA3 D10 D10 D1 D1 FWE_N FWE_N D16 D16 A11 D28 D28 A4 WP_N D23 D23 A8 D30 D30 A5 MA18 MA18 D21 D21 MA16 MA16 A3 MA19 MA19MA17 FRE_N FRE_N D19 D19 D24 D24 D9D14D7D13D11D4D6D0D15D8D5D1D12D10 MA5 CS0_N MA6MA2 MA10MA7MA21 D11D9 MA14 D14 MA13MA17 D13 MA6MA9 D15 MA12 D2D4D7 MA11MA8MA5 D3D6D0 WE_N D12D8D5 MA2 RSTOUT_N MA20MA15RD_NMA4MA22 WP WAIT# CS0_N D10D1 MA3MA19MA16MA18MA1 MA7 CS1_NLED_EN MA8MA1 MA20MA21MA22 CS1_N MA9MA0 WAIT# MA10 MA11 MA12 D2D2D2D2 RSTOUT_N MWE1_NMWE0_N MA13 D3D3D3D3RD_N LED_EN MA14 WE_N A0 MA15 WE_N RD_N GPIO82 GPIO82 GPIO87A16A10A15 MA4MA5MA8MA9 A4A5A8A9 WE3_N MWE3_N WE2_N MWE2_N WE0_N WE2_N WE1_NWE3_N MA16MA12MA13 A16A15A12A13 MA15MA6MA3MA2MRDWR_N A6A3A2 RDWR_N A2 MA14MA11MA10MA7 A11A7A10A14 A13 MA0MA1 A0A1 A1A12 CLK_MCKOMWE1_N WE0_N MWE0_N WE1_N CKO MA5 6 D4 6 MA6 6 MA7 6 D5 6 MA8 6 MA9 6 D0 6 MA10 6 RSTOUT_N 3,6,9 D6 6 D1 6 MA11 6 D7 6 MA12 6 D8 6 MA13 6 D9 6 MA14 6 D10 6 D2 6 MA15 6 MWE1_N 6 RSTOUT_N 3,6,9 MWE0_N 6 D11 6 D3 6 MA0 6 D12 6 MA1 6 LED_EN 3 D13 6 MA2 6 CS1_N 6 D14 6 RD_N 6 MA3 6 D15 6 MA4 6 WE_N 6 GPIO82 10 GPIO87 5 +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V C170.1uF U3 32MB 1 2 3 45 6 78 9 1011 12 13 14 151617181920212223242526 27 28 2930313233343536373839 40 41 42 43 4445 46 4748 49 5051 52 53 54 VDD3 DQ0 VDDQ1 DQ1DQ2 VSSQ1 DQ3DQ4 VDDQ2 DQ5DQ6 VSSQ2 DQ7 VDD1 LDQMWE#CAS#RAS#CS#BA0BA1A10/APA0A1A2A3 VDD2 VSS1 A4A5A6A7A8A9A11A12CKECLKUDQM N.C/RFU VSS2 DQ8 VDDQ4 DQ9 DQ10 VSSQ4 DQ11DQ12 VDDQ3 DQ13DQ14 VSSQ3 DQ15 VSS3 C2 0.1uF R2 NC + CT322uF C14 0.1uF v1.4 U1A JZ4730 C16 B16A16 D17C17 B17A17 C18 B18A18B19A19A20B20 C19C20 J18J19J20 K18K19K20 L18L19L20 M17M18M19M20 N17N18N19 A10C11E17E18E19E20F17F18F19F20G17G18G19G20H18H19H20B11A11D12C12B12A12C13B13A13 B14 C14 B15 C15 A14 D15D18 B9C9A8B8C8A7B10C10A15D16D19D20 A9 C7B7D7 D0D1D2D3D4D5D6D7D8D9D10D11D12D13D14D15D16D17D18D19D20D21D22D23D24D25D26D27D28D29D30D31 A0A1A2A3A4A5A6A7A8A9 A10A11A12A13A14A15A16A17A18A19A20A21A22A23A24A25 DCS0#DCS1#/GP82RAS#CAS#CKOCKERDWR# CS0# CS1#/GP83CS2#/GP84CS3#/GP85CS4#/GP86CS5#/GP87 RD#/POE WE#/PWE# WE0#/PIOW# WE1#/PIOR# WE2#/PREG# WE3# WAIT#/PWAIT# FRE#/GP79 FWE#/GP80 FRB#/GP81 RS3 33 + CT122uF U2 32MB 1 2 3 45 6 78 9 1011 12 13 14 151617181920212223242526 27 28 2930313233343536373839 40 41 42 43 4445 46 4748 49 5051 52 53 54 VDD3 DQ0 VDDQ1 DQ1DQ2 VSSQ1 DQ3DQ4 VDDQ2 DQ5DQ6 VSSQ2 DQ7 VDD1 LDQM WE# CAS#RAS# CS# BA0BA1 A10/AP A0A1A2A3 VDD2 VSS1 A4A5A6A7A8A9 A11A12 CKE CLK UDQM N.C/RFU VSS2 DQ8 VDDQ4 DQ9DQ10 VSSQ4 DQ11DQ12 VDDQ3 DQ13DQ14 VSSQ3 DQ15 VSS3 U4 K9F1G08U0B-Y TSOP48 12345 6 789 101112 13 141516171819202122232425 2627282930313233343536 37 3839404142434445464748 NC1NC2NC3NC4NC5 GND R/B#RE#CE#NC6NC7VCC1 VSS1 NC8NC9CLEALEWE#WP#NC10NC11NC12NC13NC14NC15 NC16 NC17NC18 I/O0I/O1I/O2I/O3 NC19NC20NC21 VSS2 VCC2 NC22NC23NC24 I/O4I/O5I/O6I/O7 NC25NC26NC27NC28 C8 0.1uF RS1 33 C11 0.1uF C5 0.01uF C12 0.1uF SST39VF160/320/640 U5 SST39VF640 123456789 1011 12 13 1415 1617181920212223242526 27 28 29303132333435363738394041424344454647 48 A15A14A13A12A11A10A9A8A19A20WE# RST# A21 WP# NC A18A17A7A6A5A4A3A2A1A0CE# VSS OE# DQ0DQ8DQ1DQ9DQ2 DQ10 DQ3 DQ11 VDD DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15 VSS NC A16 R1 33 C160.1uF RN4 33 1234 5678 RS4 33 C10 0.1uF C13 0.1uF C6 0.1uF C15 0.1uF RN5 33 1234 5678 RN2 33 1234 5678 R510k R3 33 C4 0.1uF RS2 33 R6 0/NC R4 10k C1 0.1uF C9 0.01uF RN1 33 1234 5678 C7 0.1uF R57 4.7K + CT222uF RN3 33 1234 5678 C3 0.1uF 55 44 33 22 11 D D C C B B A A For USB Clock USB JTAG & UART DEBUG Interface 1.0 SHOGO Digital Photo Frame Custom 210 Wednesday, August 15, 2007 TitleSize Document Number Rev Date: Sheet of LCD_CLSLCD_PSLCD_HSYNCLCD_REVLCD_VSYNC USB_CLK_EN USB_CLK_EN USB0_D-USB1_D- DMNS1DMNS0 DMNS0 USB0_D+USB1_D+ OVCR0 DPLS1 DPLS1USB_CLK USB_CLK DPLS0 DPLS0 CHARG_STAT I2C_SDAI2C_SCK GPIO100 RXD3 MII_TXD3MII_CRSMII_RXD2MII_MDCMII_RX_CLKMII_RX_ERMII_RXD0MII_TX_CLKMII_TXD1MII_TXD2MII_RX_DVMII_RXD1MII_COLMII_TXD0MII_RXD3MII_TX_EN GPIO101 TXD3 GPIO102 IIS_SDATA_IN GPIO103 PWM0 GPIO104 RTC_IRQ_INT LCD_D10LCD_D9LCD_D8LCD_D7 OVCR0 LCD_DELCD_D15LCD_D14LCD_D13LCD_D0 GPIO27_INTA IIS_RESET LCD_D6LCD_D5 GPIO105 LCD_D4LCD_D3LCD_D2LCD_D1LCD_D12LCD_D11 MII_MDIO IIS_LRCKIIS_SDATA_OUTIIS_MCLKIIS_SCLK DMNS1 SSI_CLK GPIO99 GPIO108GPIO109 SSI_CE1_NSSI_DT AUDIO_EN GPIO13_XD_CD LCD_SPL SSI_DR TCKTMSJTAG_RSTTXD3TRST_NTDORXD3TDI DC_DETE DC_DETE IIS_SDATA_INIIS_LRCKIIS_SDATA_OUTIIS_MCLKIIS_SCLKI2C_SCKIIS_RESET TCKTMSTRST_NTDI TDO CHARG_STAT I2C_SDA PENIRQ_N JTAG_RST SSI_CLKSSI_CE1_NSSI_DRSSI_DT RF_GPIO92RF_GPIO91RF_GPIO90 RF_GPIO88RF_GPIO89HV_TEST HV_TEST GPIO64 PCLK LCD_PCLK RTC_IRQ_INT 3 GPIO99 6 GPIO100 6 GPIO101 6 GPIO102 6 GPIO103 6 GPIO104 6 GPIO105 6 USB0_D- 10USB0_D+ 10USB1_D- 10USB1_D+ 10 LCD_PS 8 LCD_CLS 8 LCD_SPL 8 LCD_REV 8 LCD_HSYNC 8 LCD_VSYNC 8 PWM0 8 GPIO27_INTA 6GPIO13_XD_CD 4 LCD_D1 8 LCD_D2 8 LCD_D3 8 LCD_D4 8 LCD_D5 8 LCD_D6 8 LCD_D7 8 LCD_D8 8 LCD_D9 8 LCD_D10 8 LCD_D11 8 LCD_D12 8 LCD_D13 8 LCD_D14 8 LCD_D15 8 LCD_DE 8 LCD_D0 8 GPIO109 4 GPIO108 4 AUDIO_EN 5 MII_TXD0 9MII_TXD1 9MII_TXD2 9MII_TXD3 9 MII_TX_EN 9 MII_RX_DV 9MII_RX_ER 9 MII_RX_CLK 9 MII_RXD0 9MII_RXD1 9MII_RXD2 9MII_RXD3 9 MII_MDC 9 MII_MDIO 9 MII_COL 9 MII_CRS 9 MII_TX_CLK 9 IIS_MCLK 5IIS_S…

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ABCD DCBA Scale Sheet Size FCSM No. DWG No. Rev 1 of 1 D1 V1 BEIJING LHWT MICROELECTRONICS INC.ADDRESS: 18/F, QUANTUM PLAZA, NO.27 ZHI CHUN RD., HAI DIAN DISTRICT, BEIJINGPOST: 100083TEL: (8610)82357408/09/10/11FAX: (8610)82357412WT4+AL2230S MINIPCI C184NC L114 0.1uH + C1861uF C18310nF R46 0 INPUT 1 GND 2 SHTDN 3 N/C 4 OUTPUT 5 U12 XC6204B182MR + C1791uF VCC33 VDD33V DGND VDD18V DGND DGND GNTBIDSELFRAMEB R2710kR2810kR1310k VDD33V C120100nF C199100nF C191100nF C192100nF C193100nF DGND VDD18V AVDD33V C202100nF C203100nF C204100nF C205100nF VDD33V TX_INTX_IPTX_QNTX_QP C18710nF + C18210uF + C17610uF C17710nF C200100nF C195100nF C196100nF L109L110L111L108 DGND AGND DGND DGND DGND DGND AGND R19120 R21120 R23120 R45120 R22120 R33120 AGNDAGND VDD18VVDD33V AVDD33V DGND RSTBCLK40ME2PDIE2PCSE2PSKE2PDOTCKTRSTTMSTDITDO CS 1 SK 2 DI 3 DO 4 VCC 8 NC 7 ORG 6 GND 5 U10AT93C46-10TU_1.8 DGND VDD33V E2PCSE2PSKE2PDIE2PDO DGND PVSS2W 1 PVDD1W 18 PVSS1W 19 PVDD1W 27 PVSS1W 28 PVDD2W 32 PVSS2W 33 PVDD5APW 48 PVSS5APW 49 PVDD1W 62 PVSS1W 63 PVDD1W 65 PVSS1W 66 PVSS1W 81 PVDD1W 82 PVDD2W 83 PVSS2W 84 PVSS2W 112 PVDD2W 113 PVSS1W 114 PVDD1W 115 PVDD2W 128 POWER REFERENCE U_TDO 69 U_TDI 70 U_TMS 71 U_TRST 72 U_TCK 73 pad_S_SD_RD 85 pad_S_SCLK 86 pad_S_CS 87 pad_S_SD_WR 88 pad_TST_OBSV_MOD 89 pad_CLK_IN 90 pad_TST_MOD2 91 pad_TST_MOD1 92 pad_TST_MOD0 93 pad_RST_X_IN 106 pad_POWER_SAVE_OUT_0 64 U9AWT4_2006.01 RSTB R2610k VDD33V AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31 R30 33 PCLK IDSELDEVSELBINTABCBE0BCBE1BCBE2BCBE3BSTOPBTRDYBFRAMEBIRDYBPAR pad_P_AD_OUT_14 2 pad_P_AD_OUT_13 3 pad_P_AD_OUT_12 4 pad_P_AD_OUT_11 5 pad_P_AD_OUT_10 6 pad_P_AD_OUT_9 7 pad_P_AD_OUT_8 8 pad_P_CBEN_0 9 pad_P_AD_OUT_7 10 pad_P_AD_OUT_6 11 pad_P_AD_OUT_5 12 pad_P_AD_OUT_4 13 pad_P_AD_OUT_3 14 pad_P_AD_OUT_2 15 pad_P_AD_OUT_1 16 pad_P_AD_OUT_0 17 pad_P_IDSEL 94 pad_P_AD_OUT_31 95 pad_P_AD_OUT_30 96 pad_P_AD_OUT_29 97 pad_P_AD_OUT_28 98 pad_P_AD_OUT_27 99 pad_P_AD_OUT_26 100 pad_P_AD_OUT_25 101 pad_P_CBEN_3 102 pad_P_AD_OUT_24 103 pad_P_AD_OUT_23 104 pad_P_AD_OUT_22 105 pad_P_AD_OUT_21 107 pad_P_AD_OUT_20 108 pad_P_AD_OUT_19 109 pad_P_AD_OUT_18 110 pad_P_AD_OUT_17 111 pad_P_CBEN_2 116 pad_P_FRAMEN 117 pad_P_IRDYN 118 pad_P_TRDYN 119 pad_P_CLK 120 pad_P_DEVSELN 121 pad_P_INTN 122 pad_P_STOPN 123 pad_P_PAR_OUT 124 pad_P_AD_OUT_16 125 pad_P_CBEN_1 126 pad_P_AD_OUT_15 127 PCI INTERFACE U9BWT4_2006.01 R2910kR1410k VDD33V TCKTRSTTMS R1510k TDI R16 0 DGND INTAB R3410k pad_B_0 20 pad_B_1 21 pad_B_2 22 pad_B_3 23 pad_B_4 24 pad_B_5 25 pad_B_6 26 pad_RXHP 29 pad_A_RX_ENA 30 pad_SHDN_OUT 31 U_pad_AVS_RXI_A_ADC 34 U_pad_RB_RXI_A_ADC 35 U_pad_RT_RXI_A_ADC 36 U_pad_A_RXBBI_neg 37 U_pad_A_RXBBI_pos 38 U_pad_VCM_RXI_A_ADC 39 U_pad_AVD_RXI_A_ADC 40 U_pad_AVS_RXQ_A_ADC 41 U_pad_RB_RXQ_A_ADC 42 U_pad_RT_RXQ_A_ADC 43 U_pad_A_RXBBQ_neg 44 U_pad_A_RXBBQ_pos 45 U_pad_VCM_RXQ_A_ADC 46 U_pad_AVD_RXQ_A_ADC 47 U_pad_AVS_VGA_DAC 50 U_pad_VGA_GAIN_pos 51 U_pad_VGA_GAIN_neg 52 U_pad_AVD_VGA_DAC 53 U_pad_AVS_TXQ_DAC 54 U_pad_TXBBQ_pos 55 U_pad_TXBBQ_neg 56 U_pad_AVD_TXQ_DAC 57 U_pad_AVS_TXI_DAC 58 U_pad_TXBBI_pos 59 U_pad_TXBBI_neg 60 U_pad_AVD_TXI_DAC 61 pad_TR_SW 67 pad_TR_SW_BAR 68 pad_RF_CS 74 pad_RF_SCLK 75 pad_RF_SD_OUT 76 pad_A_TX_ENA 77 pad_PA_PE_11A 78 pad_PA_PE_11G 79 pad_RADIO_PE_OUT 80 ANALOG INTERFACEU9CWT4_2006.01 GC1GC2GC3GC4GC5GC6GC7RXHPRXONPLLON2.4GPA_ON5GPA_ONTXONDATACLKLEANTSEL1ANTSEL0 AGNDAVDD33VV_RBV_RTV_CMRX_INRX_IPAGNDAVDD33VV_RBV_RTV_CMRX_QNRX_QPAVDD33VAGNDTX_QPTX_QNAVDD33VAVDD33VAGNDAGNDTX_IPTX_IN R17 NC R18 NC AGND L9 0.1uH AVDD33V AGND + C110uF DGND C261uF 2.4GPA_ON5GPA_ON R470 R4NC PAON VDD18V R2449.9 R32 1.74K AGND 1.75V VDD18V R25560 R35 1.27K AGND 1.25V VDD18V R3115 R36 78.7 AGND V_CM A_OUT 1 A- 2 A+ 3 V- 4 B+ 5 B- 6 B_OUT 7 V+ 8 U11LMV358MM AVDD33V AGND 1.75VV_RT 1.25V V_RB 1.5V DGND C24100nF AGND C281uF AGND C5100nF AGND C25100nF AGND TST_MOD0TST_MOD1TST_MOD2 TST_MOD1 R12 0 DGND R10 NC VDD33V TST_MOD0 R11 NC DGND R2 0 VDD33V TST_MOD2 R37 0 DGND R38 NC AGND VIN 1 GND 2 ENB 3 BP 4 VOUT 5 U3AME8801CEEV C5110nF AGND VCC_2V8 C57NC C5810uF AGND AGND AGND VCC33 C5910uF AGND OE 1 GND 2 OUT 3 VDD 4 U4SQ5O04000FBCNC AGND R8300 C531nF C5610pF FREF AGND C54100nF C5510uF GC2 1 GC3 2 GC4 3 GC5 4 RFIN 5 VCCFE 6 GC6 7 GC7 8 RFOUTN 9 RFOUTP 10 VCCPA3 11 PAON 12 VCCPA2 13 VCCPA1 14 PDOUT 15 VCCPD 16 TXON 17 TX_IP 18 TX_IN 19 TX_QP 20 TX_QN 21 VREF12 22 PLLON 23 TPOUT 24 FREF 25 LE 26 CLK 27 DATA 28 VCCDIG 29 VCCPLL 30 VCCCP 31 CP 32 VCCDIV 33 VTUNE 34 GNDVCO 35 REGCAP 36 VCCREG 37 RBIAS 38 RXHP 39 NC 40 RX_QN 41 RX_QP 42 RX_IN 43 RX_IP 44 VCCZIF 45 VCCMIX 46 RXON 47 GC1 48 GND 49 AIROHA AL2230S U1 AL2230S AGND AGND R70 R41NC VCC33 R910 VCC_2V8 R200 VCC33 PA_3V3 C6010uF AGND R40NC AGND R3933 CLK40M R4210K VCC33 VCC_2V8 C1122nF AGND R512K RXHP C10NC AGND RX_QNRX_QPRX_INRX_IPGC1RXON C18 8.2pF AGND VCC_2V8VCC_2V8 C17 22nF C15 22nF GC2 GC3 GC4 GC5 C20 3.3pF L1 1.5nH AGND RFIN VCC_2V8 C3022nF AGND GC6 GC7 PAON C22 1nF C27 100nF AGND PA_3V3 unbal 1 feed 2 bal 3 bal 4 GND 5 U2BL2012-05B2450B L2 1.5nH L31.5nH C291.0pFC331.0pF AGND PA_3V3 C35100nF AGND AGND L52.2nH C340.5pF C610.5pF AGND AGND RFOUT C23100nF PA_3V3 AGND C19100nF PA_3V3PDOUT R65.6K C21NC AGND VCC_2V8 C1610nF C148.2pF TXONTX_IPTX_INTX_QPTX_QNPLLON FREF LE CLK DATA VCC_2V8 C7 100nF AGND C622nF AGND C6210uF VCC_2V8 C4 100nF AGND VCC_2V8 R1NC C2 3.3nF R30 AGND C310pF AGND VCC_2V8 C8 8.2pF AGND C910uF IN 1 OUT 2 G1 3 G2 4 FL1 LCB22M2450B1 RFIN C458.2pF AGNDAGND RXEN 4 ANT 5 RXEN 6 RX 1 GND 2 TX 3 S1HWS314 RFOUT AGND C398.2pFC468.2pF RXONTXON AGNDAGND C37NC C138.2pF AGND AGND R48NC PCLK AGND L7NC 3 12 J1MM9329-2700RA1 AGND AGND TIP 1 RING 2 NC 3 NC 4 NC 5 NC 6 NC 7 NC 8 NC 9 NC 10 NC 11 NC 12 NC 13 NC 14 CHSGND 15 NC 16 INTB# 17 +5V 18 3.3V 19 INTA# 20 NC 21 NC 22 GROUND 23 3.3VAUX 24 CLK 25 RST# 26 GROUND 27 3.3V 28 REQ# 29 GNT# 30 3.3V 31 GROUND 32 AD[31] 33 PME# 34 AD[29] 35 NC 36 GROUND 37 AD[30] 38 AD[27] 39 3.3V 40 AD[25] 41 AD[28…

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Note: This report shall not be reproduced except in full, without the written approval of Sintek Laboratory CO., Ltd. This document may be altered or revised by Sintek Laboratory Co., Ltd. personnel only, and shall be noted in the revision section of the document. Page 1 of23 FCC 47 CFR PART 15 SUBPART C TEST REPORT For RealEase Limited Digital Photo Frame Model: SG080, SG081，SG081A Trade Name: SHOGO Prepared for RealEase Limited 15/F, Morrison Commercial Building, 31 Morrison Hill Road, Wanchai Hong Kong Prepared by SINTEK LABORATORY CO., LTD. No. 7, XINSHIDAI INDUSTRIAL, GUANTIAN VILLAGE, SHIYAN TOWN, BAOAN DISTRICT, SHENZHEN, GUANGDONG, P.R.C. TEL: 86-755-27604866 FAX: 86-755-27608359 Page 2 TABLE OF CONTENTS 1. TEST RESULT CERTIFICATION............................................................................................. 3 2. EUT DESCRIPTION .................................................................................................................... 4 3. TEST METHODOLOGY ............................................................................................................. 5 3.1 EUT CONFIGURATION...................................................................................................................5 3.2 EUT EXERCISE...............................................................................................................................5 3.3 GENERAL TEST PROCEDURES........................................................................................................5 3.4 FCC PART 15.205 RESTRICTED BANDS OF OPERATIONS....................................................6 3.5 DESCRIPTION OF TEST MODES......................................................................................................6 4. INSTRUMENT CALIBRATION................................................................................................. 7 5. FACILITIES AND ACCREDITATIONS ................................................................................... 8 5.1 FACILITIES....................................................................................................................................8 5.2 EQUIPMENT...................................................................................................................................8 5.3 LABORATORY ACCREDITATIONS AND LISTING.............................................................................8 6. SETUP OF EQUIPMENT UNDER TEST .................................................................................. 9 6.1 SETUP CONFIGURATION OF EUT....................................................................................................9 6.2 SUPPORT EQUIPMENT ............................................................................................................9 7. FCC PART 15.249 REQUIREMENTS...................................................................................... 10 7.1 BAND EDGES MEASUREMENT ...........................................................................................10 7.2 RADIATED EMISSIONS................................................................................................................13 7.3 POWER LINE CONDUCTED EMISSIONS........................................................................................20 8. APPENDIX 1 PHOTOGRPHS OF TEST SETUP ................................................................... 23 Page 3 1. TEST RESULT CERTIFICATION Applicant: RealEase Limited 15/F, Morrison Commercial Building, 31 Morrison Hill Road, Wanchai, Hong Kong Equipment Under Test: Digital Photo Frame Tra de Na me : SHOGO Model: SG080，SG081，SG081A Date of Test: Nov2 ~27, 2007 Report No. : ST0710037 FCC ID : VTXSG08 APPLICABLE STANDARDS STANDARD TEST RESULT FCC Part 15 Subpart C No non-compliance noted We hereby certify that: The above equipment was tested by SINTEK LABORATORY CO., LTD. The test data, data evaluation, test procedures, and equipment configurations shown in this report were made in accordance with the procedures given in ANSI C63.4: 2001 and the energy emitted by the sample EUT tested as described in this report is in compliance with the requirements of FCC Rules Part 15.249. The test results of this report relate only to the tested sample identified in this report. Approved by: Reviewed by: Page 4 2. EUT DESCRIPTION Product Digital Photo Frame Tra de Name SHOGO Model Number SG080, SG081, SG081A Model Discrepancy N/A Power Supply DC 5.0V by adapter Frequency Range 2410 ~ 2480 MHz Antenna Specification The EUT’S antenna is integrated on the main PCB Number of Channels 71 Channels Note: This submittal(s) (test report) is intended for FCC ID: VTXSG08 filing to comply with Section 15.249 of the FCC Part 15, Subpart C Rules. Page 5 3. TEST METHODOLOGY The tests documented in this report were performed in accordance with ANSI C63.4 and FCC CFR 47 2.1046, 2.1047, 2.1049, 2.1051, 2.1053, 2.1055, 2.1057, and 15.249. 3.1 EUT CONFIGURATION The EUT configuration for testing is installed on RF field strength measurement to meet the Commissions requirement and operating in a manner that intends to maximize its emission characteristics in a continuous normal application. 3.2 EUT EXERCISE The EUT was operated in the engineering mode to fix the TX frequency that was for the purpose of the measurements. According to its specifications, the EUT must comply with the requirements of the Section 15.249 under the FCC Rules Part 15 Subpart C. 3.3 GENERAL TEST PROCEDURES Conducted Emissions The EUT is placed on the turntable, which is 0.8 m above ground plane. According to the requirements in Section 13.1.4.1 of ANSI C63.4: 2001, Conducted emissions from the EUT measured in the frequency range between 0.15 MHz and 30MHz using CISPR Quasi-peak and average detector modes. Radiated Emissions The EUT is placed on a turn table, which is 0.8 m above ground plane. The turntable shall rotate 360 degrees to determine the position of maximum emission level. EUT is set …

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TEST SETUP PHOTOS Applicant: RealEase Limited FCC ID: VTXSG08 LINE CONDUCTED EMISSION TEST RADIATED EMISSION TEST