NP4MCUB5QIntegra-TR DL3412

Integra T e c h n i c a l M a n u a l Version: Integra-TR S e r v i c e INTEGRA-TR WIRELESS MODEM Part No. 242-40V8-XYZ Copyright 1999 by Dataradio Inc. Part Number: 001-4008-101/102 Revision 5 June 2001 Dataradio COR Ltd. designs and manufactures radios and wireless modems to serve a wide variety of data communication needs. Dataradio produces equipment for the fixed data market including SCADA systems for utilities, petrochemical, waste and fresh water management markets and RF boards for OEM applications in the Radio Frequency Data Capture market. PRODUCT WARRANTY The manufacturer's warranty statement for this product is available from Dataradio COR, Ltd. 299 Johnson Avenue, Box 1733, Waseca, MN 56093-0833. Phone (507) 833-8819. The information in this document is subject to change without notice. is a trademark of DATARADIO, Inc. SECTION 1 PRODUCT OVERVIEW 1-1 001-4008-101/102 1.1 SCOPE OF MANUAL This document provides the information required for the operation and preventive maintenance of the D ATARADIO Integra-TR wireless modem. This manual is intended for system designers, installers and maintenance technicians 1.2 GENERAL DESCRIPTION Integra-TR is a high-speed transparent wireless modem. It is FCC refarming compliant and designed specifically to fit the needs of SCADA, telemetry and control applications. Integra-TR provides the communication links to data equipment for installations where wired communication is impractical. Integra-TR works with most makes and models of remote terminal units (RTU) and programmable logic controllers (PLC) and their protocols. Configuration settings allow tailoring for a variety of applications. Integra-TR supports: 1. Point to point Master-Remote or Peer-to-Peer configurations in simplex or half-duplex modes. 2. Point to multipoint Master-Remote configuration in simplex or half-duplex modes and offers full-duplex in dual-unit configuration. Settings and connections for these configurations are given later in this manual 1.2.1 CHARACTERISTICS Integra-TR has the following characteristics: z Selectable network speeds of 4800 and 9600 b/s for half channel units as well as 4800, 9600 and 19.200 b/s for full channel units. 2400 or 4800 b/s for quarter channel units z Backward compatible with the Integra-T for bit rate of 4800 and 9600 b/s (full channel units only) z One COM port for connection to DTE. Speed of 300 - 19200 bauds z One Setup port, for configuration and diagnostics (speed fixed to 9600 baud, 8 bit, no parity, 1 stop bit) z Built-in 5-watt transceiver, operating in the VHF, UHF or 900 MHz communications bands. Half-duplex or simplex operation z Fully transparent operation with error-free data delivery z Allows transmission of “break” characters z DOX (Data Operated Transmit) or RTS mode z Stations may be set as “master” or “remote” to prevent remote stations from hearing each other in a simplex RF configuration z Full local and remote diagnostics z Two 8-bit analog inputs (0 - 10V) z Low power consumption modes: “sleep” and “suspend” modes (< 20 mA). z “12 VDC, negative ground” device. 1-2 Part No. 001-4008-101/102 1.2.2 ACCESSORIES AND OPTIONS * For extended-transmit applications, the “TX Time out” timer must be turned off (set to “disable”) via the Field Programming Software. For information on accessories and options, contact your sales representative. In the United States phone 1- 800-992-7774. For international sales, phone 1-952-882-5529 or 1-305-829-4030. 1.2.3 FACTORY MUTUAL NI KIT The Integra-TR with the Factory Mutual NI Kit (DRL part number 023-1000-200) is approved as nonincendive for Class I, Groups ABCD, Division 2, hazardous locations by Factory Mutual Research Corporation. This option includes approval for International Electrotechnical Commission (IEC) Class I, Zone 2. Approved models are labeled with this rating. Only units with the Factory Mutual approved label carry the nonincendive rating. Installation, service, and repair of the FM approved units must be in accordance with the instructions found in this manual and the National Electrical Code (ANSI-NFPA 70) Division 2: Hazardous (classified) Location Incendive Wiring Techniques. Mount the unit in an enclosure or assembly. Route all interconnecting cables (DC power and coaxial) through conduit as specified in the National Electrical Code document referenced above. For further guidance on installation, see ANSI\ISA-RPI2.6: Installation of Intrinsically Safe Systems for Hazardous (Classified) locations. Figure 1-1 FM Approved External Connections AccessoryDRL Part Number Integra-TR Field Programming Kit (includes software and technical manual on CD ROM, and programming cable - DRL part number 697-4008-408) 250-4008-001 SMA Male - BNC Female adapter cable023-3410-098 *Cooling fan - factory option (For extended duty-cycle transmit applications) Catalog number plus “F” suffix. Power cable697-4008-001 Factory Mutual NI Kit023-1000-200 *Full-duplex base station - Y-cable optionContact Technical Service User Interface Cable Data Port Programming Port To Antenna System (SMA Connection) 1-3 Part No. 001-4008-101/102 Figure 1-2 Installation Dimensions 1-4 Part No. 001-4008-101/102 1.2.4 INTEGRA-TR CE Important Notice/Warning on restrictive use in all EU and EFTA member states: This device is a VHF/UHF Radio data transmitter intended for indoor and outdoor use. Operation of this device is subject to end-user licence. The end user is strongly advised to contact the local frequency management authorities to obtain such an end-user licence according to local legislations and frequency allocations. The manufacturer takes no responsibility for any unauthorized use of this device. Avis important/Avertissement au sujet de restrictions d’utilisation applicables à l’intérieur d’un pays membre de l’UE ou de l’AELE : Cet appareil est un émetteur radio opérant en VHF/UHF, d’usage intérieur ou extérieur, utilisé pour la transmission de données. L’opération de cet appareil est assujettie aux te…

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FCC ID: NP4MCUB5Q FCC Correspondence Reference Number: 19852 Form 731 Confirmation Numbe r: EA101316 QUESTION 1) The rated frequency stability shown on FCC Form 731 is 1 ppm. which is acceptable only for mobile units. This device does not appear to be designed for use "while in motion". Please resolve this issue. RESPONSE: It is correct that the primary intended use of this equipment is not ‘while in motion’, but in a ‘fixed’ application. The measurements for frequency stability in the original report show that the unit is within the 0.5 ppm stability requirement (90.213) for fixed equipment in the 403 – 512 MHz band. The measured worst case stability is 0.348 ppm at 50 °C. Form 731 originally stated 1.0 ppm because that is the manufacturer’s specification for the TCXO (Temperature Compensated Xtal Oscillator). To ensure compliance even with a worst case TCXO stability of ± 1 ppm (± 512 Hz at 512 MHz), our occupied bandwidth is designed to be at least 1200 Hz narrower (± 600 Hz from center) than required by Mask E. To show compliance, modulated spectrum occupancy was measured at temperatures from –30 °C to 60 °C in 10 °C increments against Mask E for all operational temperatures. This data is shown in the original report. We request that the Form 731 frequency tolerance be changed to 0.5 ppm to reflect the demonstrated performance of the equipment, and that type acceptance be granted for fixed operation. QUESTION 2) The attenuation requirement under Section 90.210(e)(3) is 55 + 10Log(P) which equates to 62 dB for this device at high power (5 W) and 55 dB at low power (1 W). Your test data results for radiated spurious emissions show non-compliance with these limits. Please resolve this issue. RESPONSE: The test data in the original report was incorrectly measured to the wrong specification limits. Modification was made to the unit to improve shielding of a connector that was causing non-compliance with the correct specification. The radiated spurious data was re-measured and the unit now meets the FCC requirement. The recorded data is included at the end of this response. QUESTION 3) For FM modulation , we normally use the generic formula of 2M + 2Dk for necessary bandwidth (Bn) as provided under Section 2.202(g)(III-A)(2). For k=1, the necessary bandwidth for operation of this device at 4800 bps would be 6.9 kHz and for operation at 2400 bps would be 8.08 kHz. However, "k" may be variable depending on the conditioning of the waveform. This allows for the reduction of the above values to be 6 kHz and in compliance with the authorized bandwidth limit. The value for "occupied bandwidth", i.e. 99% of the emitted spectrum is used when this value exceeds the Bn value. We propose to list this device with the single entry of 6K00F1D to cover both modes of operation. RESPONSE: We agree that a single entry of 6K00F1D is a reasonable representation of the required occupied bandwidth for this device for both modes of operation. Please make the necessary changes to the Form 731 emission designator and grant type acceptance for 6K00F1D. Integra-TR DL3412ENGINEERING REPORT - bodyPage 2 of 5 Dataradio © FCC s ubmission NAME OF TEST:Field Strength of Spurious Radiation RULE PART NUMBER:2.1033 c(14), 2.1041, 2.1053, 90.210 (d)(3) MINIMUM STANDARD:For 5 Watts; 55+10Log 10 (5) = -62 dBc For 1 Watt; 55+10Log 10 (1) = -55 dBc TEST RESULTS:Meets minimum standard (see data on the following page) TEST CONDITIONS:Standard Test Conditions, 25 C TEST PROCEDURE:TIA/EIA - 603, 2.2.12 Test Equipment:Dipole Antenna Kit, Electro-Mechanics Model 3121C Load, Tenuline Model 8340-200 ( 20 dB ) Spectrum Analyzer, HP 8563E Reference Generator, HP83732A Power Meter, HP437A MEASUREMENT PROCEDURE:Radiated spurious attenuation was measured according to TIA/EIA Standard 603 Section 2.2.12 TEST SET- UP: PERFORMED BY:_______________________________ DATE: 7/10/01 Allen Frederick SPECTRUM ANALYZER POWER METER REFERENCE GENERATOR LOAD TEST UNIT REF ERENCE ANTENNA REC EI VING ANTENNA 10 ft. Integra-TR DL3412ENGINEERING REPORT - bodyPage 3 of 5 Dataradio © FCC s ubmission Freqency:450MHz Minimum Spec = -55.0dBc Power:1Watt=30.0dBm Worse Case = -65.9dBc Spuri ousSubstitutio nAntennaCircularSpuri ous FrequencyPolarizationSpuri ousGenera torCable LossGainPolarizationAttenuation (MHz)(Horz/Vert)Level (dBm)(dBm)(dB)(dBd)Correction (dB)dBc 900H-66.3-29.65.17-1.150.0-65.9 V-69.4-29.95.17-1.150.0-66.2 1350H-76.7-32.36.001.203.0-70.1 V-74.7-29.36.001.203.0-67.1 1800H-91.7-45.56.671.203.0-84.0 V-94.4-46.56.671.203.0-85.0 2250H-85.2-33.78.001.203.0-73.5 V-90.7-40.58.001.203.0-80.3 2700H-88.0-33.18.671.203.0-73.6 V-94.2-41.28.671.203.0-81.7 3150H-88.5-30.610.001.203.0-72.4 V-89.9-32.410.001.203.0-74.2 3600H-93.0-33.211.301.203.0-76.3 V-93.5-34.611.301.203.0-77.7 4050H-95.0-32.012.501.203.0-76.3 V-94.2-32.312.501.203.0-76.6 4500H-95.7-31.512.501.203.0-75.8 V-97.5-34.112.501.203.0-78.4 Freqency:450MHz Minimum Spec = -62.0dBc Power:5Watts=37.0dBm Worse Case = -65.9dBc Spuri ousSubstitutio nAntennaCircularSpuri ous FrequencyPolarizationSpuri ousGenera torCable LossGainPolarizationAttenuation (MHz)(Horz/Vert)Level (dBm)(dBm)(dB)(dBd)Correction (dB)dBc 900H-60.6-23.95.67-1.150.0-67.7 V-63.7-24.25.67-1.150.0-68.0 1350H-68.1-23.76.501.203.0-69.0 V-66.0-20.66.501.203.0-65.9 1800H-87.4-41.27.001.203.0-87.0 V-90.2-42.37.001.203.0-88.1 2250H-80.6-29.18.671.203.0-76.6 V-84.9-34.78.671.203.0-82.2 2700H-83.2-28.39.331.203.0-76.4 V-89.4-36.49.331.203.0-84.5 3150H-86.9-29.011.001.203.0-78.8 V-88.5-31.011.001.203.0-80.8 3600H-85.4-25.612.501.203.0-76.9 V-86.0-27.112.501.203.0-78.4 4050H-89.7-26.713.331.203.0-78.8 V-89.0-27.113.331.203.0-79.2 4500H-93.7-29.514.001.203.0-82.3 V-95.7-32.314.001.203.0-85.1 Integra-TR DL3412ENGINEERING REPORT - bodyPage 4 of 5 Dataradio © FCC s ubmission CALCULATIONS FOR FIELD STRENGTH OF SPURIOUS RADIATION TESTS: The transmitter carrier frequency was 450.000 MHz. The reference oscillator frequency of all the transceivers used is 17.50 M…

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Integra-TR DL3412 Engineering Report – Annex C Page 1 of 4 06/11/01 ID Label 1. Label identification and place: right side, closest to power connector. Integra-TR DL3412 Engineering Report – Annex C Page 2 of 4 06/11/01 External Photos 1. Overview: showing left, rear, and top 2. Front view 3. Back View Integra-TR DL3412 Engineering Report – Annex C Page 3 of 4 06/11/01 Internal Photos 1. Top assembly, showing bottom of RF Board and top of Modem. 2. Bottom assembly, showing top of RF Board and bottom of Modem. Integra-TR DL3412 Engineering Report – Annex C Page 4 of 4 06/11/01 3. Exploded view: showing top of modem, top of RF Board, and separating plate.

Integra-TR DL3412Engineering Report – Annex CPage 1 of 1 06/22/01 External Photos 1. Overview: showing left, rear, and top 2. Front view 3. Back View

Integra-TR DL3412Engineering Report – Annex CPage 1 of 1 06/22/01 ID Label 1. Label identification and place: right side, closest to power connector.

Integra-TR DL3412Engineering Report – Annex CPage 1 of 2 06/22/01 Internal Photos 1. Top assembly, showing bottom of RF Board and top of Modem. 2. Bottom assembly, showing top of RF Board and bottom of Modem. Integra-TR DL3412Engineering Report – Annex CPage 2 of 2 06/22/01 3. Exploded view: showing top of modem, top of RF Board, and separating plate.

SECTION 6 CIRCUIT DESCRIPTION 6-1 001-4008-101/102 6.1 OVERVIEW Section 6 describes the circuit operation of the logic board. This section is intended for use by engineering and service personnel. 6.2 CIRCUIT DESCRIPTION Refer to Figure 6-1 for the block diagram of the Integra-TR Logic Board. 6.2.1 MICROPROCESSOR CIRCUIT The microprocessor contains two Z84015 CMOS low power Intelligent Peripheral Controllers (IPC). Each IPC is an 8-bit microprocessor integrated with CTC, SIO, PIO Clock Generator Controller and Watch Dog Timer. One of the Z84015s (U17) is used in the normal mode. The other Z84015 (U21) is used in the evaluation mode and only the CTC, SIO and PIO sections are used. The CPU section is disabled. The first Z84015 Clock Generator uses a 19.6608 MHz crystal that provides a CPU clock rate of 9.8304 MHz for both Z84015s. The 9.8304 MHz clock is further divided by 2 to feed all 8 CTC (4 in each Z84015). The 64K-memory space of the Z84015 is divided into two blocks of 32k each. The lower 32K are used for the firmware program and the upper 32K by the CMOS RAM (U18). The memory IC used for the program is a CMOS FLASH (U22) with 1024 sectors of 128 bytes each. The dual Z84015 circuit provides up to 8 Counter Timer Channels (CTC), 4 Serial Input/Output (SIO) and 32 Parallel In-put/Output (PIO) lines. The CPU also provides the clock for the CPLD modem. 6.2.2 RS232 The RS232 IC (U15) is used to interface the application DE-9 connector to the SIO_B section of U17, and the set-up DE-9 connector to the SIO_A section of U21. Two receivers remain enabled in sleep mode to ensure fast wakeup. 6.2.3 MODEM The modem section is used to interface the serial digital data to the transceiver. The CPLD modem IC (U16) with a programmable Raise-Cosine filter (U10) operates in DRCMSK mode at 2400, 4800, 9600, and 19200 bits/sec. It incorporates a 7-bit hardware scrambler and uses Differential (NRZI) encoding in DRCMSK mode to minimize data pattern-sensitivity. An electronic potentiometer U5B 6-2 Part No. 001-4008-101/102 (E-Pot), controlled by CPU U17, is used to set the transmitter deviation by amplitude adjustment of the baseband signal. Electronic potentiometer U5C is also provided to fine adjust the RF carrier frequency. 6.2.4 TRANSMIT & RECEIVE DATA Transmit Data from the RS-232 port is level-shifted to TTL by U15 and passed through the CPU for further processing and conversion from asynchronous to synchronous format. The CPLD modem, U16, takes the digital data stream from SIO-A of the CPU and synthesizes to the constant-amplitude analog baseband signal. The synthesized data stream is filtered by U10, buffered by U9B, and applied to radio module TXA at P1-6. Received signals are applied to the RXA pin on P1-13 and amplified by U3A. U3A gain is set by the electronic potentiometer, U5D, and filtered by U10. The same filter circuit is used for transmission and reception. Two analog multiplexer/demultiplexer gates (U8A and B) controlled by TX_EN line are used for sharing. The filter U10 cut-off frequency is programmable by the CPLD, based on the data rate. The analog signal is buffered by U1D and fed to Peak Detectors U3C, U3D, and U3B, and to slicer circuit U1C via U1B. The raw data is passed to the CPLD modem (U16) for de-scrambling and receive clock recovery. The resulting synchronous bit stream is fed to CPU SIO-A for further processing and conversion to asynchronous format before delivery to the RS-232 driver and to the user port. 6.2.5 INTEGRA-TR A/D AND DIGIPOT An 8 channel, 8-bit successive approximation A/D converter, type ADC0838 (U4), is interfaced to CPU (U17) and Peripheral (U21). CH0 and CH1 are connected to the positive and negative peak detector of the modem section. The software can read the positive or negative value of an RX signal, or using the differential mode, the actual peak-to- peak RX signal value. CH3 is used to measure the radio RSSI signal which was amplified by U7A. CH4 is connected to the radio diagnostic signal (P3-14). This pin is used to output an analog signal corresponding to the power output and the reflected signal. CH5 is connected to U6 (LM50), a temperature sensor with a -40 to +125°C range. CH6 is used to read the SWB+ voltage after proper scaling into the 0-5 V range. CH7 and CH8 are connected to EXT SIGNAL 1 and 2. A 2:1 divider and protection circuit is inserted between both external signals and the A/D. The External Signal (pins 1 and 2) is also connected to U21 at PB6 and PB7 through transistors Q3 and Q4 and can be used for Analog Input or Digital Output. EXT_SIGNAL 2 is also connected to the Rx test point RX-TP through U8A (74HC4066). Under software control, the RX-TP (scaled down by 2) is available on the power connector for trouble-shooting purposes. A 4-channel digital potentiometer type (U5) is used to adjust the RX Signal, TX Modulation, Carrier Frequency and Carrier Detect Threshold. 6-3 Part No. 001-4008-101/102 An 8 channel, 8-bit successive approximation A/D converter, type AD0838 (U9), is interfaced to CPU (U18) and Peripheral (U20). U19 generates a power-on reset for the CPU and U6 is a temperature sensor used by the firmware to compensate for variations in RSSI. The RSSI signal from the transceiver is amplified and filtered by U7A. The signal is compared to a threshold value set by digital potentiometer (U5A). The output of the comparator (U7B) is used to change the hold time of both peak detectors at the beginning of the receive packet. 6.2.6 WAKE-UP CIRCUIT The wake-up circuit for the Integra-TR consists of a 50 ms monostable circuit that is triggered by the rising edge of a Sleep signal from CPU (U17). The falling edge of this 50 ms pulse (end of pulse) is connected to the NMI of the CPU and will wake up the CPU from Sleep mode after 50 ms. When exiting SLEEP mode on a \NMI, the CPU firmware will increment a counter, then return to Sleep until it reaches a limit set by a software parameter. When the programmed count is reached the CPU will w…

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SECTION 4 4-1 Part No. 001-3412-201/202 CIRCUIT DESCRIPTION 4.1 INTRODUCTION The main subassemblies of this transceiver are the RF board, VCO board, PA module, and TCXO. A block diagram of the transceiver is located in Figure 4-1. The VCO board is enclosed by a metal shield and soldered directly to the RF board. The VCO is not field serviceable. Return the transceiver to the Dataradio factory for repairs. The 3412 has a reference oscillator stability of ±1.5 PPM. The 17.5 MHz TCXO (Temperature Compensated Crystal Oscillator) is soldered directly to the RF board. The TCXO is not field serviceable. Return the transceiver to the Dataradio factory for repairs. 4.2 GENERAL OPERATION 4.2.1 SYNTHESIZER / VCO The VCO (voltage-controlled oscillator) output signal is the receiver first injection frequency in the Receive mode and the transmit frequency in the Transmit mode. The first injection frequency is 52.95 MHz above the receive frequency. The frequency of this oscillator is controlled by a DC voltage produced by the phase detector in synthesizer chip U811. Channels are selected by programming counters in U811 to divide by a certain number. This programming is performed over a serial bus formed by the Synth Clock, Synth Enable, and Data pins of J201. This programming is performed by the user supplied hardware/software (see Section 3). The frequency stability of the synthesizer in both the receive and transmit modes is established by the stability of the reference oscillator described in the preceding section. These oscillators are stable over a temperature range of -30° to +60° C (-22° to +140° F). 4.2.2 RECEIVER The receiver is a double-conversion type with intermediate frequencies of 52.95 MHz / 450 kHz. Two helical bandpass filters reject the image, half IF, injection, and other unwanted frequencies. A four-pole crystal filter and an 8-pole ceramic filter enhance receiver selectivity 4.2.3 TRANSMITTER The transmitter produces a nominal RF power output of 5W at 13.3V DC, adjustable down to 1W. Frequency modulation of the transmit signal occurs in the synthesizer. Transmit audio processing circuitry is contained in the Loader board or customer-supplied equipment. CIRCUIT DESCRIPTION 4-2 Part No. 001-3412-201/202 Figure 4-1 Transceiver Block Diagram Z201 RF AMP Z202 MIXER CRYSTAL FILTER PREDRIVER ANTENNA SWITCH RX AUDIO VCO AMPLIFIER T/R PS SYNTHESIZER VCO BUFFER/ RSSI LOW-PASS FILTER RF OUT RF BPFRF BPF U221 Z221/Z222 52.95 MHz IF / 450 kHz FILTER Q401 2nd LO TRIPLER/AMP 1st LO AMP CLV Q853 Q851/Q852 AMPLIFIER RSSI RX OUT TX IN Y801 TCXO MOD INPUT MOD ADJUST SYNTH OUT RF IN U811 BUFFER U241 Q301 IF AMP Q850 U521 TRANSMITTER RECEIVER +13.3V +4.6V U581B U581A PWR SET DIAG DIAG EN MOD ADJ DIAG DIAG EN TX EN +9V TX RX EN +13.3V SWITCHED CLOCK DATA ENABLE LOCK Q122 Q121 Q801 TEST -2.0V Q171 Q841, Q842 Q901, Q902 Q501 Q701 Q123 +5V DC SHUTDOWN Q511 Q531/U111C CR561/562 V FWD V REV U913C U913A U912 U261 Q131/U131 U141 +9.6V +5.5V Q231Q211Q201/Q202 Q101/Q102 U111A/B/D Q124 U911 RSSI RX OUT TX EN CLOCK DATA Q172 Q173 +9.6V RECEIVE CIRCUIT DESCRIPTION 4-3 Part No. 001-3412-201/202 4.3 SYNTHESIZER / VCO A block diagram of the transceiver is shown in Figure 4-1 and a block diagram of Synthesizer IC U811 is shown in Figure 4-2. As stated previously, the synthesizer output signal is produced by a VCO (voltage controlled oscillator). The VCO frequency is controlled by a DC voltage produced by the phase detector in U811. The phase detector senses the phase and frequency of the two input signals and causes the VCO control voltage to increase or decrease if they are not the same. The VCO is then “locked” on frequency. Programming of the synthesizer provides the data necessary for the internal prescaler and counters. One input signal is the reference frequency. This frequency is produced by the 17.5 MHz reference oscillator (TCXO). The other input signal is the VCO frequency. Figure 4-2 U811 Synthesizer Block Diagram CLOCK DATA STROBE Vss RF IN RF IN 64/65/72 PRESCALER MAIN DIVIDERS EM FB 22128 PRNM1 NM3 NM2 FRACTIONAL ACCUMULATOR PRESCALER MODULUS CONTROL 3 FMOD NF FB SERIAL INPUT + PROGRAM LATCHESV DD TEST IN REF EM+EA REFERENCE DIVIDER+2+2+2 MAIN MAIN PHASE DETECTOR REFERENCE SELECT 2 SM EM REFERENCE SELECT 2 SA SECONDARY PHASE DETECTOR EA AUXILIARY IN EA AUX 12 NR 12 NAPA AUXILIARY DIVIDER PRESCALER 1/4 NORMAL OUTPUT CHARGE PUMP OUTPUT CHARGE PUMP SPEED-UP OUTPUT CHARGE PUMP INTEGRAL OUTPUT CHARGE PUMP AUXILIARY CN 8 CL 2 CK 4 2 V SSA V DDA LOCK PHA RA PHI PHP RN RF CIRCUIT DESCRIPTION 4-4 Part No. 001-3412-201/202 4.3.1 VOLTAGE-CONTROLLED OSCILLATOR The VCO is formed by Q850, several capacitors and varactor diodes, and ceramic resonator Z850. It oscillates at the transmit frequency in transmit mode and first injection frequency in the receive mode (380-512 MHz in transmit and 432.950-564.950 MHz in receive). Biasing of Q850 is provided by R862, R867, and R868. An AC voltage divider formed by C859, C861, C862, and Z850 which initiates and maintains oscillation and also matches Q850 to the tank circuit. The VCO frequency is controlled in part by DC voltage across varactor diodes CR854, CR855, CR856 and CR851. As voltage across a reverse-biased varactor diode increases, its capacitance decreases; VCO frequency increases as the control voltage increases. CR854/CR855 and CR856/CR851 are paralleled varactors to divide the capacitance and improve linearity. The varactors are biased at -2.0V so the control line can operate closer to ground. The control line is isolated from tank circuit RF by choke L851/L854 and decoupling capacitor C854. The amount of frequency change produced by CR854/CR855/CR856/CR851 is controlled by series capacitor C853. The -2.0V applied to the VCO is derived from the 17.5 MHz TCXO frequency that is amplified by Q701, rectified by CR701 and filtered by C706, C707, C708 and C709 on the RF board. 4.3.2 VCO AND REFERENCE OSCILLATOR MODULATION Both the VCO and reference oscillator (TCXO) are mo…

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DL-3412 TUNE-UP PROCEDURE Ref: FCC Part 2 paragraph 2. 1033(c)(9) 1. Connect the transceiver to be aligned to a DC power source. A DC current meter capable of measuring at least 2.5 Amps should be connect in line with the DC source. Connect the output of the transceiver through a watt meter and into a 50 ohm dummy load. 2. Load the synthesizer with the center channel frequency. 3. Key the transmitter and make certain that the supply voltage at the RF board is 13.3 VDC. (Do not transmit for extended periods of time. ) 4. Adjust R535 clockwise for 5.0 Watts of output power. 5. Check the power levels on the low and the high frequencies for 5.0 Watts +/- 1 Watt. DL-3412 ACTIVE CIRCUITS DESCRIPTION Designator Function JEDEC or Vendor Type CR561 Antenna switch MMBV3401 CR562 Antenna switch MMBV3401 CR591 Directional coupler MMBD701LT1 CR592 Directional coupler MMBD701LT1 CR701 Rectifier BAV99LT1 CR851 Varactor BB535E7908 CR852 Varactor BB515 CR853 Deviation level bias BB515 CR854 Varactor BB535E7908 CR855 Varactor BB535E7908 CR856 Varactor BB535E7908 CR901 Varactor BB535E7908 Q101 Tx enable MUN5213T1 Q102 Tx enable MUN5114T1 Q121 Rx enable MUN5213T1 Q122 Rx enable MUN5213T1 Q123 Rx enable MUN2114T1 Q124 Soft key up control PZT2222AT1 Q131 5 volt shutdown MUN5213T1 Q171 Pin shift MUN5213T1 Q172 Pin shift MUN2114T1 Q501 RF buffer MSA-2111 Q511 RF driver NE85633 Q531 Power control PZT2222AT1 Q701 Amplifier MMBT918LT1 Q801 Constant voltage source MDS1819A-RT1 Q841 Pin Shift MUN5231T1 Q842 Pins shift MUN5114T1 Q850 VCO NE85619 Q851 Cascode amp NE85619 Q852 Cascode amp NE85619 Q853 Amplifier NE85619 Q901 Capacitance multiplier MDS1819A-RT1 U111A Soft key up control LMC660AIM U111B Soft key up control LMC660AIM U111C Power control LMC660AIM U111D Soft key up control LMC660AIM U131 Voltage regulator TK11900MTL U141 Voltage regulator TK11900MTL U581A V-fwd amp MC33172DT U581B V-rev amp MC33172DT U811 Synthesizer SA7025DK-T U521 RF power module M57721M INTEGRA R 210-3315-XXX ACTIVE CIRCUITS DESCRIPTION Designator function Type D1 DIODE, HOT CARRIER, SOT-23 MMBD301LT1 D2 DIODE, HOT CARRIER, SOT-23 MMBD301LT1 D3 DIODE, SOT-23 BAV99LT1 D4 DIODE, SOT-23 BAV99LT1 D5 DIODE, SOT-23 BAV99LT1 D6 DIODE,RECTF,1A/100V 1N4001 DS1 LED,3MM,BICOLOR,RED/GREEN SMT 591-3001-102 DS2 LED,3MM,BICOLOR,RED/GREEN SMT 591-3001-102 DS3 LED,3MM,BICOLOR,RED/GREEN SMT 591-3001-102 DS4 LED,3MM,BICOLOR,RED/GREEN SMT 591-3001-102 Q1 TRANSISTOR, GENERAL PURPOSE,SOT-23 MMBT3904LT1 Q2 TRANSISTOR, GENERAL PURPOSE,SOT-23 MMBT3904LT1 Q3 TRANSISTOR, GENERAL PURPOSE,SOT-23 MMBT3904LT1 Q4 TRANSISTOR, GENERAL PURPOSE,SOT-23 MMBT3904LT1 U1 QUAD, OP-AMP , -40/+85 SO-14 TLC2274ID U2 HEX INVERTER CMOS 74HC04AD U3 QUAD OP-AMP LMC6484AIM U4 8 BIT A/D,-40/+85C SO-20W ADC0838CIWM U5 POTENTIOMETER 4 DIGITAL AD8403AR50 U6 TEMPERATURE SENSOR,SOT-23 LM50CIM3 U7 DUAL OP-AMP,-40/+85 S0-8 TLC2272ID U8 ANALOG MULTIPLEXERS/DEMULTIPLEXERS SOIC16 MC74HC4053D U9 QUAD, OP-AMP , -40/+85 SO-14 TLC2274ID U10 FILTER, LINEAR PHASE LOW PASS S0-8 LTC1069-7 U11 REGULATOR,MICROPOWER VOLTAGE ,S0-8 LP2951CD U12 REGULATOR,LOW DROPOUT,Q PACKAGE LT1129IQ-5 U13 DUAL MONOSTABLE, SOIC 74HC4538AD U14 QUAD NAND GATE 74HC00AD U15 CONVERTER RS-232 ADM223AR U16 ( TO BE PROGRAMMED) CPLD 64 MACROCELL PZ5064-I12A44 U17 MICROPROCESSOR ,10MHz Z8401510FEC U18 RAM,CMOS,32K x 8, -40/=85, SOP-28 TC55257DFI-85L or TC55257DFL-85L (SCREENED -40 +85) U19 RESET CIRCUIT, -40+85 ,S0-8 MC33064D-5 U20 HEX OR GATE,CMOS 74VHC32AD U21 MICROPROCESSOR ,10MHz Z84C1510FEC/Z8401510FEC U22 (TO BE PROGRAMMED) EPROM, FLASH 1 MEGABIT, -40/+85 PLCC AT29C010A-90J1 X1 XTAL, FPX SERIES 19.6608 MHz FPX196-20PF

11 22 33 44 55 66 77 88 A A B B C C D D R103 33R R93 33R R120R108 R142 100K U21 Z84C1510FEC A0 6 A1 5 A2 4 A3 3 A4 2 A5 1 A6 100 A7 99 A8 98 A9 97 A10 96 A11 95 A12 94 A13 93 A14 92 A15 91 D0 89 D1 88 D2 87 D3 86 D4 85 D5 84 D6 83 D7 82 PA0 29 PA1 28 PA2 27 PA3 26 PA4 25 PA5 24 PA6 23 PA7 22 PB0 53 PB1 54 PB2 55 PB3 56 PB4 57 PB5 58 PB6 59 PB7 60 W/RDYA 30 SYNA 31 RXDA 32 RXCA 33 TXCA 34 TXDA 35 DTRA 36 RTSA 37 CTSA 38 DCDA 39 W/RDYB 52 SYNCB 51 RXDB 50 RXCB 49 TXCB 48 TXDB 47 DTRB 46 RTSB 45 CTSB 44 DCDB 43 WDOUT 73 A7RF 70 CSO 40 CSI 42 RFSH 7 M1 8 RST 9 BSREQ 10 WAIT 11 BUSACK 12 WR 13 RD 14 IORQ 15 MREQ 17 HALT 18 INT 19 NMI 63 EV 67 XTAL1 65 XTAL2 66 CKOUT 68 CKIN 69 ARDY 20 ASTB 21 BRDY 62 BSTB 61 CK0 81 CK1 80 CK2 79 CK3 78 TO0 74 TO1 75 TO2 76 TO3 77 IEO 71 IEI 72 5V 41 5V 90 GND 16 GND 64 R121 R73 100K R110R122 R136 33R P7 SFM-120-01-D-A (MATE WITH TFM-120-31-D-A) 13579111315171921232527293133353739 40383634323028262422201816141210 8642 R123R111 P6 TSW-106-07-G-S 123456 R106 33R R132 33R C560.1uF R137 33R P1 HEADER 8 Pin …

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