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AR5001AP - AR5311 BASED 802.11a ACCESS POINT REVISION NUMBERINITIALSDESCRIPTION EAInitial external release.245-01080-030 DATE 3/28/02 ATHEROS CONFIDENTIAL PRELIMINARY VNRF TRIM245-01080-0314/15/02 VNAdd 0.5 pF Caps around Ethernet ports.245-01080-0404/17/02 245-01080-0414/18/02EACorrected part numbers for D3,F5,Q3,U1,U3; updated R3 to 1%. Updated Title block titles. 5/15/02EA245-01080-042Added clarification notes, NC'd AR5311 EE pins, changed XG1 to 25MHz 7/3/02245-01080-050VNAdded C349, 22 pF, 0402 at DLY_0. Added C350, C, 0402 at U8 pin 68. 8/1/02Moved voltage input circuit.(page8 to page10)XV-5850 VER 0.4 Added switching power circuit and XI-1250 wireless LED (DS9) at page 10. Changed DS4 part and delete DS5 at page 7. Added JP3 part and R171 at page 9. DNS : Do Not Serial Updated R113,R137 2.0K,1% to 2K,5% Updated R59,R111-112,R114-116,R147,R157-160 5.11K,1% to 5.1K,5% Updated R106,R117,R129,R132,R161 365,1% to 330,5% Added DS6-1 0805 LED at page 9. RESET MONITOR PRELIMINARY EJTAG Flash SDRAM Only one Reset monitor is required. Dual footprint inlcuded for flexibility. ATHEROS CONFIDENTIAL 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 10 13 37 46 27 12 47 11 28 26 14 15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 VCC GND GND RESET BYTE WE OE CE WP/ACC RY/BY 1 2 1 1 2 1 2 1 1 1 2 1 2 4 6 8 10 12 14 1 3 5 7 9 11 13 1 2 1 1 2 1 2 1 2 1 2 1 2 12 1 2 1 1 1 2 1 2 1 2 1 4 3 RESET GND Vcc MR 1 2 1 2 1 2 2 4 5 7 8 10 11 13 22 23 24 25 26 27 45 47 48 50 51 53 54 56 68 77 60 61 62 63 64 65 66 74 76 79 80 82 83 85 31 33 34 36 37 39 40 42 12 6 32 38 46 52 78 84 1 15 29 43 3 9 35 41 49 55 75 81 18 67 19 17 20 16 71 28 59 21 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 BA0 BA1 A10 A0 A1 A2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CLK DQ10 A3 A4 A5 A6 A7 A8 A9 DQ8 DQ9 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CAS CKE RAS WE CS DQM0 DQM1 DQM2 DQM3 A11 1 2 AR5311 Memory Interface UX1A AR5311 H2 G1 G2 C2 D2 D3 E3 F3 H3 K3 H1 K2 AB1 J2 J1 P2 N3 F1 B3 N2 N1 AA1 AB2 Y2 W2 V2 U2 U1 T2 T1 R2 R1 R3 U3 V1 V3 W1 W3 Y1 F2 E1 E2 D1 C1 B1 A1 A2 B6 A5 B5 A4 B4 A3 C5 C4 M2 L1 L2 K1 M1 AB3 P1 AB4 AA4 AB9 Y9 AA9 AA8 AB7 Y6 AA6 AB5 Y4 Y8 AB8 Y7 AA7 AB6 Y5 AA5 AA3 C6 MEM_ADDR0 MEM_ADDR1 MEM_ADDR2 MEM_ADDR3 MEM_ADDR4 MEM_ADDR5 MEM_ADDR6 MEM_ADDR7 MEM_ADDR8 MEM_ADDR9 MEM_ADDR10 MEM_ADDR11 MEM_ADDR12 MEM_ADDR13 MEM_ADDR14 MEM_ADDR15 MEM_ADDR16 MEM_ADDR17 MEM_ADDR18 MEM_ADDR19 MEM_ADDR20 MEM_ADDR21 MEM_ADDR22 SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 SD_DATA4 SD_DATA5 SD_DATA6 SD_DATA7 SD_DATA8 SD_DATA9 SD_DATA10 SD_DATA11 SD_DATA12 SD_DATA13 SD_DATA14 SD_DATA15 SD_DATA16 SD_DATA17 SD_DATA18 SD_DATA19 SD_DATA20 SD_DATA21 SD_DATA22 SD_DATA23 SD_DATA24 SD_DATA25 SD_DATA26 SD_DATA27 SD_DATA28 SD_DATA29 SD_DATA30 SD_DATA31 SD_CLK SD_DLY_OUT SD_DLY_IN SD_CS_L SD_CKE MEM_CS0_L MEM_WE_L FL_OE_L FL_CS_L FL_BOOTMODE FL_DATA0 FL_DATA1 FL_DATA2 FL_DATA3 FL_DATA4 FL_DATA5 FL_DATA6 FL_DATA7 FL_DATA8 FL_DATA9 FL_DATA10 FL_DATA11 FL_DATA12 FL_DATA13 FL_DATA14 FL_DATA15 MEM_CS1_L 1 2 1 1 2 2 1 1 2 1 2 1 2 2 1 1 2 12 1 2 1 2 1 2 4 32 1 VCC OUTGND EN 1 2 1 12 1 2 1 2 1 1 2 2 1 4 3 RESET GND Vcc MR 12 1 1 2 1 2 1 2 1 2 1 2 1 2 12 AR5311 System Signals UX1D AR5311 F22 F21 F20 H20 J20 Y13 AA13 Y14 A6 C7 B8 B7 A7 C8 A8 A9 B9 C9 M21 M22 N22 L22 L21 G22 G21 G20 D20 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 TCLK TMS TDO TDI TRST_L EJTAG_SEL BAUD_CLK PROC_REF_CLK PROC_CLK_SEL NMI SYS_RESET COLD_RESET_L PROC_WARM_RESET LED0 LED1 NC1 NC3 NC2 NC0 ATHEROS CONFIDENTIALPRELIMINARY D:\5G\XV5850\XV5850 v04.dsn 0.4 AR5001AP - AR5311 MII and AR5111 Interface C 310 Monday, September 02, 2002 TitleSize Document Number Rev Date: Sheet of ANTAXLNAON_L RADIO_DATA3/RF_RESET TXSW PLLBYPASS XPAB CLK32 SHIFTLOAD ADCISEL RADIO_DATA2 RFDATAIN RADIO_DATA1 RX_CLEAR U0_RTSU0_CTS CTRL2XLNAON RADIO_DATA0 RFSHIFTRFRESET_LRFLOAD M0_TXD1M0_RXD3 M0_RXERR M0_TXD2 M0_COL M0_TXD3M0_RXD0M0_RXD2 M0_TXCM0_TXD[0:3] M0_RXD1M0_TXD0 M0_RXD[0:3]M0_CRS/M0_RESETM0_TXENM0_RXC ADCRES XPAA /U0_DSR/U0_RI/U0_DCD U0_SOUTU0_SIN U1_SINU1_SOUT M0_MDCM0_MDIO CTRL1 DACIPDACINDACQPDACQN RFDATAOUT3 RFDATAOUT[0:3] RFDATAOUT2RFDATAOUT0 ADCP_QADCP_IADCN_IADCN_Q RFDATAOUT1 M1_COLM1_TXCM1_TXEN/M1_RESETM1_MDIOM1_RXDVM1_RXERRM1_CRSM1_MDC M1_TXD3M1_TXD1M1_RXD2M1_TXD2 M1_RXC M1_TXD0M1_RXD1M1_RXD0M1_RXD3 M0_RXDVM1_TXD[0:3]M1_RXD[0:3] RFDATAIN 4 CLK32 4 U0_SOUT 9 U0_SIN 9 U0_RTS 9 U0_CTS 9 XLNAON 5CTRL2 5CTRL1 5RFSHIFT 4 RFLOAD 4RFRESET_L 4 M0_RXD[0:3] 7 M0_COL 7M0_RXERR 7 /M0_RESET 7M0_CRS 7M0_TXD[0:3] 7M0_RXDV 7M0_TXC 7M0_TXEN 7M0_RXC 7 XPAA 5 M0_MDC 7M0_MDIO 7 DACN_I 4DACP_I 4DACN_Q 4DACP_Q 4 ADCP_Q 4ADCP_I 4ADCN_I 4ADCN_Q 4RFDATAOUT[0:3] 4 M1_TXC 10M1_MDC 10/M1_RESET 10M1_RXDV 10M1_RXC 10M1_RXERR 10 M1_TXEN 10M1_COL 10M1_CRS 10M1_MDIO 10M1_TXD[0:3] 10M1_RXD[0:3] 10 3.3V 3.3V 3.3V R68 33 TP15 1 R66365 1% R8410K 12 R636.19K 1% R67365 1% TP2 1 R81 33 C1208.2pF TP4 1 C10622pF R961K 12 C1218.2pF R74 33 5311 MII and Serial Interfaces UX1BAR5311 R20P21P22P20T21U22U21V22T20R21R22U20V20W22V21T22N21N20AB22AA22Y21Y22AA20Y19AA18AB18Y18AA19AB21AB19AA17Y17AB17AB20W21W20 Y10 AB13AA12AA10AB12AB10AB11AA11AB14AA16AB16AA14 Y16 AB15 Y15 AA15 M0_RXD0M0_RXD1M0_RXD2M0_RXD3 M0_TXD0M0_TXD1M0_TXD2M0_TXD3 M0_RXERR M0_RXC M0_RXDV M0_TXEN M0_COL M0_RESET_L M0_CRS M0_TXC M0_MDC M0_MDIO M1_RXD0M1_RXD1M1_RXD2M1_RXD3 M1_RXC M1_TXD0M1_TXD1M1_TXD2M1_TXD3 M1_TXC M1_RXDV M1_TXEN M1_COL M1_RESET_L M1_CRS M1_RXERR M1_MDC M1_MDIO U0_SINU0_SOUTU0_RTS_L U0_DCD_LU0_DSR_LU0_CTS_LU0_DTR_LU0_RI_LU1_SINU1_SOUTU1_RTS_LU1_CTS_LU1_DSR_LU1_DTR_LU1_DCD_LU1_RI_L R82 33 R92R 12 AR5311 Radio Interface UX1CAR5311 B14A14B12A12 C15C14 A18B18B16A16A22B22C21C22 D21 A20B20A21 E22 D22 K21K22H21H22E20E21J21J22 K20 ADC_INADC_IPADC_QPADC_QNADCISELADC_RES DAC_IP DAC_IN DAC_QP DAC_QN RFDATAOUT0RFDATAOUT1RFDATAOUT2RF…

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