MI7-M32450-25Data Mobile Radio

Crystal LAN TM Ethernet Controller 1 Cirrus Logic, Inc.Copyright © Cirrus Logic, Inc. 2000 P.O. Box 17847, Austin, Texas 78760(All Rights Reserved) (512) 445 7222 FAX: (512) 445 7851 http://www.cirrus.com CS8900A OVERVIEW FEATURES •Single-Chip IEEE 802.3 Ethernet Controller •Maximum Current Consumption = 55 mA (5V Supply) •3 V Operation •Industrial Temperature Range •Comprehensive Suite of Software Drivers Available •Efficient PacketPage™ Architecture Operates in I/O and Memory Space and as DMA Slave •Direct Bus Interface •Full Duplex Operation •On-Chip RAM Buffers Transmit and Receive Frames •10BASE-T Port with Analog Filters, Provides: — Automatic Polarity Detection and Correction • AUI Port for 10BASE2, 10BASE5, and 10BASE-F •Programmable Transmit Features: — Automatic Re-transmission on Collision — Automatic Padding and CRC Generation The CS8900A is a true single-chip, full-duplex, Ethernet solution, incorporating all of the analog and digital circuitry needed for a complete Ethernet circuit. Major functional blocks include: a direct bus interface; an 802.3 MAC engine; integrated buffer memory; a serial EEPROM interface; and a com- plete analog front end with both 10BASE-T and AUI. The CS8900A is a low-cost Ethernet LAN Control- ler optimized for embedded applications and Per- Functional Block Diagram EEPROM RJ-45 10BASE- T Attachment Unit Interface (AUI) 20 MHz XTA L RAM Bus Logic Memory Manager 802.3 MAC Engine EEPROM Control Encoder/ Decoder & PL L 10BASE-T RX Filters & Receiver 10BASE-T TX Filters & Transmitter AUI Transmitter AUI Collision AUI Receive r Cloc k Power Manage r Boundary Scan Test Logic LED Contro l CS8900A Ethernet Controller Bus (cont.)(cont.) NOV ‘01 PI271PP2 Product Bulletin CS8900A Crystal LAN TM Ethernet Controller 2PI271PP2 OVERVIEW(Continued from Page 1) sonal Computers. Its highly-integrated design eliminates the need for costly external components required by other Ethernet controllers. The CS8900A includes on-chip RAM, 10BASE-T trans- mit and receive filters, and a direct Bus interface with 24 mA Drivers. In addition to high integration, the CS8900A offers a broad range of performance features and config- uration options. Its unique PacketPage architec- ture automatically adapts to changing network traffic patterns and available system resources. The result is increased system efficiency. The CS8900A is available in a 100-pin TQFP package ideally suited for small form-factor, cost-sensitive Ethernet applications. With the CS8900A, system engineers can design a complete Ethernet circuit that occupies less than 1.5 square inches (10 sq. cm)ofboardspace. Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advanceproduct infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by CirrusLogic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publi- cation may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, orotherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part ofthe printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photo- graphic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc.trade- marks and service marks can be found at http://www.cirrus.com. FEATURES(Continued from Page 1) •Programmable Receive Features: — Stream Transfer™ for Reduced CPU Overhead — Auto-Switch Between DMA and On-Chip Memory — Early Interrupts for Frame Pre-Processing — Automatic Rejection of Erroneous Packets • EEPROM Support for Jumperless Configuration •Boot PROM Support for Diskless Systems •Boundary Scan and Loopback Test •LED Drivers for Link Status and LAN Activity •Standby and Suspend Sleep Modes •All the most popular drivers are available, including: — LINUX —Microsoft •NDIS2DOSdriver • NDIS 2 OS/2 driver • NDIS 3 drivers for Windows NT, Windows for Work- groups, Windows 95, and Windows CE • Novell •ODI DOS driver •ODI OS/2 driver •ODI Server •Packet Driver (TCP/IP) •pSOS •Real-time OS drivers •RIPL (Remote Initial Program Load) for ODI and NDIS 2 •RTOS/NCOS (ARM and Oracle) - In development •SCO •Setup/installation Utility: EEPROG Utility (EEPROM programming utility) •UNIX •VxWorks NOTE:To inquire about additional drivers, see“Order- ing Information” on page 3 CONFIDENTIAL DRAFT CS8900A Crystal LAN TM Ethernet Controller 3PI271PP2 OVERVIEW(cont.) CONFIDENTIAL DRAFT Key Benefits Very Low Cost The CS8900A is designed to provide the lowest- cost Ethernet solution available for embedded applications, portable motherboards, and adapter cards. Cost-saving features include: •Int…

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Trimble Key Features and Benefits • 3.3 V for battery powered applications • Programmable power management • Sized for portable devices Lassen LP GPS Low power module for portable applications Trimble’s new Lassen ™ LP GPS is a low power miniature GPS receiver module that is ideal for power-conscious portable appli- cations. It is intended specifically for system designers and integra- tors who are developing the next generation of portable devices. This embedded technology gives the system developer the programming flexibility to achieve a significant reduction in power consumption. Power management The Lassen LP GPS features a new set of power management tools that puts the power budget decision in the developer’s hands. The developer now can deter- mine the best balance between operational frequency and power conservation for a particular application. In Schedule Track ™ operat- ing mode, the developer can program the unit to power up, quickly acquire satellites and out- put position to a schedule. After gathering satellite data and com- puting its location, the receiver may be directed to power down to a minimal mode of operation for a programmed interval or until awakened by a hardware interruption. Schedule Track provides hot start performance at a programmed interval or in response to a hardware event. Schedule Track mode provides an advantage over normal battery-backed fast start modes with automatic wakeup to maintain current satellite data for fastest possible acquisition. Schedule Track offers the lowest power consumption in a deep sleep mode but provides position data as quickly as possible when needed. Ease of integration Lassen LP GPS provides a choice of data protocols for maximum flexibility. The TSIP binary data protocol incorporates new power management features and provides maximum control over system operation. The TAIP and NMEA protocols are available where ASCII data is preferred. A secondary serial input port is available for RTCM SC-104 differential correction data for high accuracy applications. The Lassen LP GPS also incorporates Trimble’s antenna detection and protection circuit to monitor the condition of the antenna system. And a new high performance, miniature 3.3 V antenna is available for the Lassen LP GPS. Getting started The Starter Kit makes it easy to evaluate the Lassen LP GPS and begin development. Actual size Lassen LP GPS Low power module for portable applications PHYSICAL CHARACTERISTICS Dimensions2.605′′L×1.250′′W×0.475′′H (66.167 mm×31.750 mm×12 mm) Weight0.4 oz. (12.5 grams) ConnectorsRF:right angle MCX Power, I/O:8-pin (2×4), 2 mm header ACCESSORIES GPS antennaCompact, 3.3 V active micropatch antenna with 5-meter cable and magnetic mount. 1.65′′×1.99′′×0.55′′high (42 mm×50.5 mm×13.8 mm) ORDERING INFORMATION Module Lassen LP GPS Module, Extended Temperature, TSIP (binary) protocol, NMEA 0183 (ASCII) protocol and TAIP (ASCII) protocol, DGPS ready Antennas 3.3 V antenna, 5-meter cable with MCX connector Starter Kit Includes Lassen LP GPS module mounted on interface motherboard in a durable metal enclosure with dual DB9, RS232 interface, AC/DC power converter, magnetic-mount 3 V antenna, TSIP, NMEA and TAIP protocols, software toolkit for TSIP, interface cable and manual. Manual Lassen LP GPS Module System Designer Reference Guide © Copyright 1999, Trimble Navigation Limited. All rights reserved. The Trimble logo with Trimble is a trademark of Trimble Navi gation Limited registered in the United States Patent and Trademark Office. Lassen and Schedule Track are trademarks of Trimble Navigation Limited. All other marks are the property of their respective own ers. TID11547C (11/99) PERFORMANCE SPECIFICATIONS GeneralL1 frequency, C/A code (SPS), 8-channel, continuous tracking receiver, 32 correlators Update rateTSIP @ 1 Hz NMEA @ 1 Hz TAIP @ 1 Hz Accuracy Position 25 m CEP (50%) w/o SA Velocity0.1 m/sec without SA Time±95 nano-seconds (over-determined clock mode) DGPS accuracy Position 2 m CEP (50%) Velocity0.05 m/sec Acquisition (typical)Cold start*:< 130 seconds (90%) Warm start**:< 45 seconds (90%) Hot start***:< 20 seconds (90%) Reacquisition after signal loss< 2 seconds (90%) Dynamics Acceleration 4 g (39.2 m/sec 2 ) Motional Jerk20 m/sec 3 Operational limitsAltitude <18,000 m or velocity < 515 m/sec either limit may be exceeded but not both ENVIRONMENTAL SPECIFICATIONS Operating temp–40°C to +85°C (standard) Storage temp–55°C to +100°C Vibration0.008 g 2 /Hz5 Hz to 20 Hz 0.05 g 2 /Hz20 Hz to 100 Hz –3 dB/octave100 Hz to 900 Hz Operating humidity5% to 95% R.H. non-condensing, + 60°C Altitude–400 m to +18,000 m TECHNICAL SPECIFICATIONS Prime power+3.3 V DC, ± 0.3 V Power consumption Normal operation GPS board only: 55 mA, 0.182 W with antenna: 67 mA, 0.221 W Deep sleep8 mA, board only Backup power+3.0 to +3.6 V DC 2–5 μA at +25°C (nominal) Serial ports/1PPSCMOS TTL levels I/O ProtocolsTSIP (binary data) NMEA 0183 v2.1 (ASCII data) TAIP (ASCII data) NMEA messagesGGA, VTG, GLL, ZDA, GSA, GSV and RMC messages selectable by TSIP command; selection stored in non-volatile memory. Antenna power3.3 V at 12 mA, feedline fault detect/protect * Cold start requires no initialization ** Warm start implies last position, time and almanac are saved in battery-backed memory *** Hot start implies ephemeris also saved. All GPS receivers are subject to degradation of position and velocity accuracies under Department of Defense imposed Selective Availability (SA). Visit our website at www.trimble.com/oem Specifications subject to change without notice. Trimble Navigation Limited Corporate Headquarters 645 North Mary Avenue Sunnyvale, CA 94086 +1-408-481-8940 +1-408-481-7744 Fax www.trimble.com Trimble Navigation Europe Limited Trimble House Meridian Office Park Osborne Way Hook, Hampshire RG27 9HX U.K. +44 1256-760-150 +44 1256-760-148 Fax Trimble Navigation Singapore PTE Limited 79 Anson Road #05-02 Singapore 079906 SINGAPORE +65-325-5668 +65-225-9989 Fax

I I P P S S e e r r i i e e s s M M 3 3 2 2 4 4 5 5 0 0 - - 2 2 5 5 M M o o b b i i l l e e R R a a d d i i o o P P r r o o d d u u c c t t O O w w n n e e r r ’ ’ s s M M a a n n u u a a l l Date Released: December 23, 2003 Document #: 516-80519-POM Revision: A Copyright 2003 IPMobileNet, Inc. 16842 Von Karman Avenue, Suite 200  Irvine, CA 92606 Voice: (949) 417-4590 Fax: (949) 417-4591 M32450-25-FCCRpt.doc Page ii The term “IC”: before the radio certification number only signifies that Industry of Canada technical specifications were met. Operation is subject to the following two (2) conditions: (1) this devise may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of this device. The following U.S. Patents apply to this product: U.S. Patent numbers 5,640,695,6,018,647,6,243,393 Information contained in this document is subject to change without notice. All rights reserved. Reproductions, adaptations, or translation without prior written permission is prohibited, except as allowed under copyright laws. TABLE OF CONTENTS M32450-25-FCCRpt.doc Page 2 SECTION 1: THEORY OF OPERATION................................................................................. 3 General Block Diagram................................................................................................ 3 General Block Diagram Definitions ..................................................................... 3 M32450-25 Mobile Radio Section Descriptions......................................................... 5 Microcontroller .................................................................................................... 5 Support Circuitry ................................................................................... 5 Inputs/Outputs .................................................................................................... 5 Modem .............................................................................................................. 6 VLogic and Digital Ground ................................................................................. 6 Receiver 1 Front-End ......................................................................................... 7 Receiver 1 IF ...................................................................................................... 7 Transmit Modulation ........................................................................................... 7 Injection Synthesizer .......................................................................................... 8 Transmitter/TR Switch ........................................................................................ 8 Power and Analog Ground ................................................................................. 8 SECTION 2: FACTORY TEST PROCEDURE......................................................................... 9 Equipment List............................................................................................................. 9 Programming and Configuring Mobile Radio.......................................................... 10 Adjustment / Alignment Procedures........................................................................ 11 Receiver Injection ............................................................................................. 11 Receiver 1 ........................................................................................................ 11 Receiver 2 ........................................................................................................ 11 Transmit Data ................................................................................................... 12 Transmit Power Control .................................................................................... 12 Receive Data .................................................................................................... 13 Final Test .......................................................................................................... 13 Uplink Hardware Timing Verification ................................................................ 15 Downlink Hardware Timing Verification ............................................................ 17 SECTION 3: FCC LABEL...................................................................................................... 19 M32450-25 Data Transceiver FCC Label Placement............................................... 19 M32450-25 Data Transceiver FCC Label.................................................................. 19 APPENDIX A: M32450-25 CIRCUIT BOARD DIAGRAMS................................................... 20 APPENDIX B: M32450-25 TEST DATA SHEET................................................................... 21 SECTION 1: THEORY OF OEPRATION M32450-25-FCCRpt.doc Page 3  General Block Diagram General Block Diagram Definitions For increased data security, the modem supports the Federal Government developed Digital Encryption Standard (DES) data encryption and decryption protocols. This capability requires installation of third party, Internet Protocol (IP) compliant DES encryption and decryption software on the system. The M32450-25 mobile radio is comprised of two (2) circuit boards, the digital board and the RF board. The digital circuit board contains the following sections: Input/Output Circuitry associated with the following data connectors: ‰ RS232 Serial Port DB9 Data Connector ‰ RJ45 Ethernet 10 Base T Interface Connector  For further details on the Ethernet Controller, refer to the Crystal LAN Ethernet Controller Product Bulletin (CS8900A-EthernetCtrlr.pdf) available on the Product Documentation CD. Microcontroller Manages the operation of the radio, the modem, and determines which receiver provides a better signal from a given transmission. Also provides transmit time-out protection in the event a fault causes the radio to halt…

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COMMUNICATION SEMICONDUCTORS MX919B DATA BULLETIN 4-Level FSK Modem Data Pump ©2001 MX•COM, INC. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. PRELIMINARY INFORMATION Features Applications • 4-Level Root Raised Cosine FSK Modulation • Half Duplex, 4800 to 19.2kbps • Increase Channel Bit Rate/Hz • Full Data Packet Framing • Impulse and NRZ Signal Modes • Enhanced Performance in Noisy Conditions • Error Detection and Error Correction • Low Power 3.3V/5.0V Operation • Wireless Data Terminals • Two Way Paging Systems • Digital Radio Systems • Wide Area Wireless Data Broadcasts • Point to Point Wireless Data Links MODEM DATA PUMP MX919B ANALOG TX DATA AND CONTROL BUS ANALOG RX RF RADIO DISCRIMINATOR MODULATOR SYSTEM APPLICATION PROCESSING HOST Cμ The MX919B is a low voltage CMOS device containing all of the baseband signal processing and Medium Access Control (MAC) protocol functions required for a high performance 4-level FSK Wireless Packet Data Modem. It interfaces with the modem host μC and the radio modulation/demodulation circuits to deliver reliable two-way transfer of the application data over a wireless link. The MX919B assembles application data received from the host μC, adds forward error correction (FEC) and error detection (CRC) information, and interleaves the result for burst-error protection. After automatically adding symbol and frame sync codewords, the data packet is converted into filtered 4-level analog signals for modulating the radio transmitter. In receive mode, the MX919B performs the reverse function using the analog signals from the receiver discriminator. After error correction and removal of the packet overhead, the recovered application data is supplied to the host μC. CRC detected residual uncorrected data errors will be flagged. A readout of the SNR value during receipt of a packet is also provided. The MX919B uses data block sizes and FEC/CRC suitable for applications where high-speed transfer of data over narrow-band wireless links is required. The device is programmable to operate at standard bit rates from a wide range of Xtal/clock frequencies. The MX919B may be used with a 3.0V to 5.5V power supply and is available in the following package styles: 24-pin SSOP (MX919BDS), 24-pin SOIC (MX919BDW), 24-pin PLCC (MX919BLH), and 24-pin PDIP (MX919BP). 4-Level FSK Modem Data Pump Page 2 of 47 MX919B PRELIMINARY INFORMATION ©2001 MX•COM, INC. www.mxcom.com Tele: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480170.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. CONTENTS Section Page 1. Block Diagram ............................................................................................................... 6 2. Signal List ...................................................................................................................... 7 3. External Components ................................................................................................... 8 4. General Description ...................................................................................................... 9 4.1 Description of Blocks ......................................................................................................... 9 4.1.1 Data Bus Buffers..................................................................................................................... 9 4.1.2 Address and R/W Decode ...................................................................................................... 9 4.1.3 Status and Data Quality Registers.......................................................................................... 9 4.1.4 Command, Mode, and Control Registers ............................................................................... 9 4.1.5 Data Buffer.............................................................................................................................. 9 4.1.6 CRC Generator/Checker ........................................................................................................ 9 4.1.7 FEC Generator/Checker ......................................................................................................... 9 4.1.8 Interleave/De-Interleave Buffer............................................................................................... 9 4.1.9 Frame Sync Detect ................................................................................................................. 9 4.1.10 Rx Input Amp ........................................................................................................................ 10 4.1.11 RRC Low Pass Filter ............................................................................................................10 4.1.12 Tx Output Buffer.................................................................................................................... 11 4.1.13 Rx Level/Clock Extraction ..................................................................................................... 12 4.1.14 Clock Oscillator and Dividers................................................................................................ 12 4.2 Modem - μC Interaction ................................................................................................... 12 4.3 Binary to Symbol Translation ........................................................................................... 13 4.4 Frame Structure............................................................................................................... 14 4.5 The Programmer’s View................................................................................................... 15 4.5.1 Data Block Buffer ........................................................…

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Front Back Top Bottom Left Right

SECTION 3: FCC LABEL M32450-25 Data Transceiver FCC Label Placement M32450-25 Data Transceiver FCC Label

Interior Overall PCB 1 Top PCB 1 Bottom PCB 2 Top PCB 2 Bottom PCB 3 Top PCB 3 Bottom

 General Block Diagram General Block Diagram Definitions For increased data security, the modem supports the Federal Government developed Digital Encryption Standard (DES) data encryption and decryption protocols. This capability requires installation of third party, Internet Protocol (IP) compliant DES encryption and decryption software on the system. The M32450-25 mobile radio is comprised of two (2) circuit boards, the digital board and the RF board. The digital circuit board contains the following sections: Input/Output Circuitry associated with the following data connectors: ‰ RS232 Serial Port DB9 Data Connector ‰ RJ45 Ethernet 10 Base T Interface Connector  For further details on the Ethernet Controller, refer to the Crystal LAN Ethernet Controller Product Bulletin (CS8900A- EthernetCtrlr.pdf) available on the Product Documentation CD. Microcontroller Manages the operation of the radio, the modem, and determines which receiver provides a better signal from a given transmission. Also provides transmit time-out protection in the event a fault causes the radio to halt in the transmit mode. Modem Converts serial data into an analog audio waveform for transmission and analog audio from the receiver to serial data. Within a single chip it provides forward error detection and correction, bit interleaving for more robust data communications, and third generation collision detection and correction capabilities. Power Supply The power supply creates the various voltages required by the digital portion of the mobile radio. The RF circuit board contains the following sections: Transmit Processing Circuitry that amplifies the analog audio signal from the modem and uses it to modulate the voltage controlled oscillator (VCO) and 10 MHz reference oscillator in the injection synthesizer section. Modulating the VCO and reference oscillator simultaneously results in a higher quality FM signal. Injection Synthesizer Provides programmable, ultra stable signals for the radio. Synthesizer incorporates phase lock loop technology used for both receiving and transmitting. Injection In the receive mode, the synthesizer provides a local oscillator signal of 45 MHz above or below the selected receive channel frequency. Transmitter Consists of an exciter and power amplifier module. The transmitter covers the various frequency bands in segments. A different power amplifier module is required for each segment. The transmitter circuitry includes a T/R switch switching the antenna between transmitter and receiver 1 (TX/RX1). Receiver 1/Receiver 2 Required to support the mobile DRS; two (2) discrete receivers are tuned to the same channel and use two (2) antennas. The receivers are double-conversion superheterodyne with a first Intermediate Frequency (IF) of 45 MHz and a second IF frequency of 455 KHz. Each receiver consists of bandpass filters, an RF amplifier, a MMIC mixer, crystal filters, and a one-chip IF system. The injection synthesizer provides the first local oscillator signal. Outputs from each receiver include RSSI and analog audio for the baseband routing circuitry and modem. Power Supply Consists of circuitry that derives the various operating voltages for the RF portion of the mobile radio.  M32450-25 Mobile Radio Section Descriptions The M32450-25 Mobile Radio works within a frequency range of 450 to 480 MHz and requires a 1/4- wavelength antenna. This section provides detailed descriptions of each of the sections within the M32450-25 Mobile Radio. Refer to Appendix A to view the M32450-25 Mobile Radio Circuit Board Diagram. Microcontroller The microcontroller (U30) is a major component of the radio as it manages the operation of the radio. It also controls the operation of the modem, and determines which receiver provides a better signal from a given transmission. It provides transmit time-out protection in the event a fault causes the radio to halt in the transmit mode. It utilizes a reduced instruction set computer (RISC) architecture which provides low power operation and a powerful instruction set. Other features include a watchdog timer, serial universal asynchronous receiver/transmitter (UART), two 8-bit timers, and 2 KB of electrically erasable programmable read only memory (EEPROM) storage. NOTE : The EEPROM Random Access Memory (RAM) stores the setup data entered by the technician even if there is a loss of power. Support circuitry The support circuitry consists of the following: ƒ A Supervisor Control Chip (U25) provides power-on reset. ƒ The clock controls microcontroller operation and is generated by crystal Y3 and a Pierce oscillator circuit (inside the U30-microcontroller). ƒ The latch (U28) decodes low order address bits (A0-A7) from the address/data bits (AD0- AD7). It is controlled by Address Latch Enable (ALE) output of U30 and the bits are used by the modem. ƒ A 512Kx8 Static RAM Chip (U31) provides temporary storage of the radio’s configuration data facilitating the technician with access to make changes. ƒ Control logic is also an important part in the microcontroller section. The RAM chip select (RAMCS*) and modem chip select (MODEMCS*) command lines are created by U26A, U27BCD, and U44ABC. These gates decode four (4) high order address bits (A11-A15). The RAM is addressed by five (5) memory addresses (MA14-MA18) bits decoded by U26D, U27A, and U24. This logic decodes port address bits (PA14-PA18) to produce memory address bits (MA14-MA18) for the RAM chip. Input/Output Input/output components convert serial and handshake data from the modem section to RS232 levels, and vice-versa. Chip U22 is an RS232 transmitter and receiver. It converts data in 5-volt logic form to data in +/-12-volt form, as required by the RS232 standard. A charge pump power supply on the chip c…

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